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2010 – 2019
- 2014
[c52]Taieb Lamine Ben Cheikh, Gabriela Nicolescu, Jelena Trajkovic
, Youcef Bouchebaba, Pierre G. Paulin:
Fast and accurate implementation of Canny edge detector on embedded many-core platform. NEWCAS 2014: 401-404- 2013
- [j21]Sébastien Le Beux, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin:
Reduction methods for adapting optical network on chip topologies to 3D architectures. Microprocess. Microsystems 37(1): 87-98 (2013) - [j20]Pierre G. Paulin, Ali Erdem Özcan, Vincent Gagné, Bruno Lavigueur, Olivier Benny:
Parallel programming patterns for multi-processor SoC: Application to video processing. ACM Trans. Embed. Comput. Syst. 12(1s): 47:1-47:25 (2013) - [c51]Claude Helmstetter, Sylvain Basset, Romain Lemaire, Fabien Clermidy, Pascal Vivet, Michel Langevin, Chuck Pilkington, Pierre G. Paulin, Didier Fuin:
A dynamic stream link for efficient data flow control in NoC based heterogeneous MPSoC. ASP-DAC 2013: 41-46 - [c50]Thierry Lepley, Pierre G. Paulin, Eric Flamand:
A novel compilation approach for image processing graphs on a many-core platform with explicitly managed memory. CASES 2013: 6:1-6:10 - [c49]Pierre G. Paulin:
Mapping data-intensive applications to an explicitly managed memory architecture: Challenges and solutions. ESTIMedia 2013: 1 - 2012
- [j19]Youcef Bouchebaba, Ali Erdem Özcan, Pierre G. Paulin, Gabriela Nicolescu:
MpAssign: a framework for solving the many-core platform mapping problem. Softw. Pract. Exp. 42(7): 891-915 (2012) - [j18]Bruno Girodias, Luiza Gheorghe Iugan, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Michel Langevin, Pierre G. Paulin:
Integrating Memory Optimization with Mapping Algorithms for Multi-Processors System-on-Chip. ACM Trans. Embed. Comput. Syst. 11(3): 64:1-64:26 (2012) - [c48]Salim Ismail Al-Akhras, Sofiène Tahar, Gabriela Nicolescu, Michel Langevin, Pierre G. Paulin:
On the Verification of a WiMax Design Using Symbolic Simulation. SCSS 2012: 23-37 - 2011
- [c47]Pierre G. Paulin:
Programming challenges & solutions for multi-processor SoCs: an industrial perspective. DAC 2011: 262-267 - [c46]Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin:
Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology. DATE 2011: 788-793 - 2010
- [j17]Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin:
Multi-Optical Network-on-Chip for Large Scale MPSoC. IEEE Embed. Syst. Lett. 2(3): 77-80 (2010) - [j16]Sébastien Le Beux, Guy Bois, Gabriela Nicolescu, Youcef Bouchebaba, Michel Langevin, Pierre G. Paulin:
Combining mapping and partitioning exploration for NoC-based embedded systems. J. Syst. Archit. 56(7): 223-232 (2010) - [c45]Sébastien Le Beux, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin:
A system-level exploration flow for optica network on chip (ONoC) in 3D MPSoC. ISCAS 2010: 3613-3616 - [c44]Youcef Bouchebaba, Pierre G. Paulin, Ali Erdem Özcan, Bruno Lavigueur, Michel Langevin, Olivier Benny, Gabriela Nicolescu:
MpAssign: A framework for solving the many-core platform mapping problem. International Symposium on Rapid System Prototyping 2010: 1-7 - [c43]Bruno Girodias, Luiza Gheorghe, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Michel Langevin, Pierre G. Paulin:
Combining memory optimization with mapping of multimedia applications for multi-processors system-on-chip. International Symposium on Rapid System Prototyping 2010: 1-9
2000 – 2009
- 2009
- [j15]Bruno Girodias, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Pierre G. Paulin, Bruno Lavigueur:
Multiprocessor, Multithreading and Memory Optimization for On-Chip Multimedia Applications. J. Signal Process. Syst. 57(2): 263-283 (2009) - [c42]Sébastien Le Beux, Gabriela Nicolescu, Guy Bois, Youcef Bouchebaba, Michel Langevin, Pierre G. Paulin:
Optimizing Configuration and Application Mapping for MPSoC Architectures. AHS 2009: 474-481 - 2008
- [c41]Simon Schliecker, Mircea Negrean, Gabriela Nicolescu, Pierre G. Paulin, Rolf Ernst:
Reliable performance analysis of a multicore multithreaded system-on-chip. CODES+ISSS 2008: 161-166 - [c40]Eshel Haritan, Toshihiro Hattori, Hiroyuki Yagi, Pierre G. Paulin, Wayne H. Wolf, Achim Nohl, Drew Wingard, Mike Muller:
Multicore design is the challenge! what is the solution? DAC 2008: 128-130 - 2007
- [j14]Andrew B. Kahng, Ira Chayut, John M. Cohn, Toshihiro Hattori, Jeong-Taek Kong, Pierre G. Paulin, Rich Tobias:
Roundtable: Design and CAD Challenges for Leading-Edge Multimedia Designs. IEEE Des. Test Comput. 24(1): 83-93 (2007) - [j13]Ahmed Amine Jerraya, Olivier Franza, Markus Levy, Masao Nakaya, Pierre G. Paulin, Ulrich Ramacher, Deepu Talla, Wayne H. Wolf:
Roundtable: Envisioning the Future for Multiprocessor SoC. IEEE Des. Test Comput. 24(2): 174-183 (2007) - [j12]Youcef Bouchebaba, Bruno Girodias, Gabriela Nicolescu, El Mostapha Aboulhamid, Bruno Lavigueur, Pierre G. Paulin:
MPSoC memory optimization using program transformation. ACM Trans. Design Autom. Electr. Syst. 12(4): 43 (2007) - [c39]Youcef Bouchebaba, Essaid Bensoudane, Bruno Lavigueur, Pierre G. Paulin, Gabriela Nicolescu:
Two-level tiling for MPSoC architecture. ASAP 2007: 314-319 - [c38]Laura Pozzi, Pierre G. Paulin:
A future of customizable processors: are we there yet? DATE 2007: 1224-1225 - [c37]Youcef Bouchebaba, Bruno Lavigueur, Bruno Girodias, Gabriela Nicolescu, Pierre G. Paulin:
MPSoC memory optimization for digital camera applications. DSD 2007: 424-427 - [c36]Karim Hadjiat, Francis St-Pierre, Guy Bois, Yvon Savaria, Michel Langevin, Pierre G. Paulin:
An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept. ICECS 2007: 995-998 - 2006
- [j11]Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Damien Lyonnard, Olivier Benny, Bruno Lavigueur, David Lo, Giovanni Beltrame, Vincent Gagné, Gabriela Nicolescu:
Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia. IEEE Trans. Very Large Scale Integr. Syst. 14(7): 667-680 (2006) - [c35]Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Olivier Benny, Damien Lyonnard, Bruno Lavigueur, David Lo:
Distributed object models for multi-processor SoC's, with application to low-power multimedia wireless systems. DATE 2006: 482-487 - [c34]Bruno Girodias, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Pierre G. Paulin, Bruno Lavigueur:
Application-Level Memory Optimization for MPSoC. IEEE International Workshop on Rapid System Prototyping 2006: 169-178 - [c33]Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Pierre G. Paulin, Essaid Bensoudane:
An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures. VLSI-SoC 2006: 146-151 - 2005
- [r1]Essaid Bensoudane, Gabriela Nicolescu, Pierre G. Paulin, Michel Langevin, Chuck Pilkington, Damien Lyonnard:
A Multiprocessor SoC Platform and Tools for Communications Applications. Embedded Systems Handbook 2005 - 2004
- [c32]Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Gabriela Nicolescu:
Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management. CODES+ISSS 2004: 48-53 - [c31]Francine Bacchini, Pierre G. Paulin, Reinaldo A. Bergamaschi, Raj Pawate, Arie Bernstein, Ramesh Chandra, Mohamed Ben-Romdhane:
System level design: six success stories in search of an industry. DAC 2004: 349-350 - [c30]Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane, Michel Langevin, Damien Lyonnard:
Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding. DATE 2004: 58-63 - [c29]Pierre G. Paulin:
DATE Panel: Chips of the Future: Soft, Crunchy or Hard? DATE 2004: 844-851 - [c28]Pierre G. Paulin:
Automatic Mapping of Parallel Applications onto Multi-Processor Platforms: A Multimedia Application. DSD 2004: 2-4 - [c27]Pierre G. Paulin:
Designing High Quality, Scaleable SoC??s with Heterogeneous Components. ISQED 2004: 325 - 2003
- [c26]Philippe Magarshack, Pierre G. Paulin:
System-on-chip beyond the nanometer wall. DAC 2003: 419-424 - [c25]Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane:
Network Processing Challenges and an Experimental NPU Platform. DATE 2003: 20064-20069 - 2002
- [j10]Pierre G. Paulin, Miguel Santana:
FlexWare: A Retargetable Embedded-Software Development Environment. IEEE Des. Test Comput. 19(4): 59-69 (2002) - [j9]Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane:
StepNP: A System-Level Exploration Platform for Network Processors. IEEE Des. Test Comput. 19(6): 17-26 (2002) - [c24]Vassilios Gerousis, Oz Levia, Pierre G. Paulin, Mark Pinto, Chris Rowen, Gabriele Saucier:
Who Owns the Platform? DATE 2002: 238 - 2001
- [c23]Pierre G. Paulin, Faraydon Karim, Paul Bromley:
Network processors: a perspective on market requirements, processor architectures and embedded S/W tools. DATE 2001: 420-429 - [c22]Pierre G. Paulin:
Embedded systems technologies for application-specific architecture platforms. ISSS 2001: 195 - [c21]Ahmed Amine Jerraya, Pierre G. Paulin, Richard Norman, Feliks J. Welfeld:
Programming models for network processors (Panel). ISSS 2001: 202 - 2000
- [c20]Rolf Ernst, Grant Martin, Oz Levia, Pierre G. Paulin, Stamatis Vassiliadis, Kees A. Vissers:
The Future of Flexible HW Platform Architectures Panel Discussion. DATE 2000: 634 - [c19]Pierre G. Paulin:
Towards Application-Specific Architecture Platforms: Embedded Systems Design Automation Technologies. EUROMICRO 2000: 1028-1029
1990 – 1999
- 1998
- [j8]Carlos A. Valderrama, François Naçabal, Pierre G. Paulin, Ahmed Amine Jerraya:
Automatic VHDL-C Interface Generation for Distributed Cosimulation: Application to Large Design Examples. Des. Autom. Embed. Syst. 3(2-3): 199-217 (1998) - 1997
- [j7]Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerraya:
Compilation Methods for the Address Calculation Units of Embedded Processor Systems. Des. Autom. Embed. Syst. 2(1): 61-77 (1997) - [j6]Clifford Liem, François Naçabal, Carlos A. Valderrama, Pierre G. Paulin, Ahmed Amine Jerraya:
System-on-a-Chip Cosimulation and Compilation. IEEE Des. Test Comput. 14(2): 16-25 (1997) - [j5]Pierre G. Paulin, Clifford Liem, Marco Cornero, François Naçabal, Gert Goossens:
Embedded software in real-time signal processing systems: application and architecture trends. Proc. IEEE 85(3): 419-435 (1997) - [j4]Gert Goossens, Johan Van Praet, Dirk Lanneer, Werner Geurts, Augusli Kifli, Clifford Liem, Pierre G. Paulin:
Embedded software in real-time signal processing systems: design technologies. Proc. IEEE 85(3): 436-454 (1997) - [c18]Clifford Liem, Marco Cornero, Miguel Santana, Pierre G. Paulin, Ahmed Amine Jerraya, Jean-Marc Gentit, Jean Lopez, Xavier Figari, Laurent Bergher:
Am Embedded System Case Study: The Firm Ware Development Environment for a Multimedia Audio Processor. DAC 1997: 780-785 - [c17]Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerraya:
ReCode: the design and re-design of the instruction codes for embedded instruction-set processors. ED&TC 1997: 612 - 1996
- [c16]Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerraya:
Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures. DAC 1996: 597-600 - [c15]Carlos A. Valderrama, François Naçabal, Pierre G. Paulin, Ahmed Amine Jerraya:
Automatic generation of interfaces for distributed C-VHDL cosimulation of embedded systems: an industrial experience. RSP 1996: 72-77 - 1995
- [j3]Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala:
DSP design tool requirements for embedded systems: A telecommunications industrial perspective. J. VLSI Signal Process. 9(1-2): 23-47 (1995) - [c14]Pierre G. Paulin, Jean Fréhel, Michel Harrand, Elisabeth Berrebi, Clifford Liem, François Naçabal, Jean-Claude Herluison:
High-level synthesis and codesign methods: an application to a videophone codec. EURO-DAC 1995: 444-451 - [c13]Clifford Liem, Pierre G. Paulin, Marco Cornero, Ahmed Amine Jerraya:
Industrial experience using rule-driven retargetable code generation for multimedia applications. ISSS 1995: 60-68 - [e2]Pierre G. Paulin, Farhad Mavaddat:
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France. ACM 1995, ISBN 0-89791-771-5 [contents] - 1994
- [c12]Shailesh Sutarwala, Pierre G. Paulin:
Flexible modeling environment for embedded systems design. CODES 1994: 124-130 - [c11]Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala:
Flexware: A flexible firmware development environment for embedded systems. Code Generation for Embedded Processors 1994: 67-84 - [c10]Clifford Liem, Trevor C. May, Pierre G. Paulin:
Instruction-Set Matching and Selection for DSP and ASIP Code Generation. EDAC-ETC-EUROASIC 1994: 31-37 - [c9]Clifford Liem, Trevor C. May, Pierre G. Paulin:
Register assignment through resource classification for ASIP microcode generation. ICCAD 1994: 397-402 - [c8]Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala:
CodeSyn: a retargetable code synthesis system (abstract). HLSS 1994: 94 - [e1]Pierre G. Paulin:
Proceedings of the 7th International Symposium on High Level Synthesis, HLSS'94, Niagra-on-the-Lake, ON, Canada, May 18-20, 1994. ACM 1994, ISBN 0-8186-5785-5 [contents] - 1993
- [c7]Shailesh Sutarwala, Pierre G. Paulin, Yatish Kumar:
Insulin: An Instruction Set Simulation Environment. CHDL 1993: 369-376 - 1991
- [c6]Ahmed Amine Jerraya, Pierre G. Paulin, Simon Curry:
Meta VHDL for Higher Level Controller Modeling and Synthesis. VLSI 1991: 215-224
1980 – 1989
- 1989
- [j2]Pierre G. Paulin, John P. Knight:
Algorithms for high-level synthesis. IEEE Des. Test 6(6): 18-31 (1989) - [j1]Pierre G. Paulin, John P. Knight:
Force-directed scheduling for the behavioral synthesis of ASICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(6): 661-679 (1989) - [c5]Pierre G. Paulin, John P. Knight:
Scheduling and Binding Algorithms for High-Level Synthesis. DAC 1989: 1-6 - [c4]Pierre G. Paulin:
Horizontal Partitioning of PLA-based Finite State Machines. DAC 1989: 333-338 - [c3]Pierre G. Paulin, Franck J. Poirot:
Logic decomposition algorithms for the timing optimization of multi-level logic. ICCD 1989: 329-333 - 1987
- [c2]Pierre G. Paulin, John P. Knight:
Force-Directed Scheduling in Automatic Data Path Synthesis. DAC 1987: 195-202 - 1986
- [c1]Pierre G. Paulin, John P. Knight, Emil F. Girczyc:
HAL: a multi-paradigm approach to automatic data path synthesis. DAC 1986: 263-270
Coauthor Index
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