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ORCIDMichael K. Gowan
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2000 – 2009
- 2009
[j2]Blaine A. Stackhouse, Sal Bhimji, Chris Bostak, Dave Bradley, Brian S. Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, Paul E. Gronowski, Dan Krueger, Charles Morganti, Steve Troyer:
A 65 nm 2-Billion Transistor Quad-Core Itanium Processor. IEEE J. Solid State Circuits 44(1): 18-31 (2009)- 2008
- [c5]Blaine A. Stackhouse, Brian S. Cherkauer, Michael K. Gowan, Paul E. Gronowski, Chris Lyles:
A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor. ISSCC 2008: 92-93 - 2002
- [c4]Joel Grodstein, Rachid Rayess, Tad Truex, Linda Shattuck, Sue Lowell, Dan Bailey, David Bertucci, Gabriel P. Bischoff, Daniel E. Dever, Mike Gowan, Roy Lane, Brian Lilly, Krishna Nagalla, Rahul Shah, Emily Shriver, Shi-Huang Yin, Shannon V. Morton:
Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU. ACM Great Lakes Symposium on VLSI 2002: 1-6
1990 – 1999
- 1998
- [j1]Paul E. Gronowski, William J. Bowhill, Ronald P. Preston, Michael K. Gowan, Randy L. Allmon:
High-performance microprocessor design. IEEE J. Solid State Circuits 33(5): 676-686 (1998) - [c3]Michael K. Gowan, Larry L. Biro, Daniel B. Jackson:
Power Considerations in the Design of the Alpha 21264 Microprocessor. DAC 1998: 726-731 - [c2]Mark Matson, Dan Bailey, Shane L. Bell, Larry L. Biro, Steve Butler, John Clouser, Jim Farrell, Mike Gowan, Donald A. Priore, Kathryn Wilcox:
Circuit implementation of a 600 MHz superscalar RISC microprocessor. ICCD 1998: 104-110 - [c1]Dilip K. Bhavsar, David R. Akeson, Michael K. Gowan, Daniel B. Jackson:
Testability access of the high speed test features in the Alpha 21264 microprocessor. ITC 1998: 487-495
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