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2010 – 2019
- 2018
[j7]Asma Benmessaoud Gabis
, Pierre Bomel, Marc Sevaux:
Application-aware Multi-Objective Routing based on Genetic Algorithm for 2D Network-on-Chip. Microprocess. Microsystems 61: 135-153 (2018)- [j6]Asma Benmessaoud Gabis, Pierre Bomel, Marc Sevaux:
Bi-Objective Cost Function for Adaptive Routing in Network-on-Chip. IEEE Trans. Multi Scale Comput. Syst. 4(2): 177-187 (2018) - 2017
- [j5]Erwan Moreac, Pierre Bomel, Johann Laurent, André Rossi:
Energy Savings in Networks-on-Chip with Smart Temporal Shielding. J. Low Power Electron. 13(3): 441-455 (2017) - [j4]Erwan Moreac, André Rossi, Johann Laurent, Pierre Bomel:
Bit-accurate energy estimation for Networks-on-Chip. J. Syst. Archit. 77: 112-124 (2017) - [c22]Erwan Moreac, Johann Laurent, Pierre Bomel, André Rossi, Emmanuel Boutillon, Maurizio Palesi:
Energy aware Networks-on-Chip cortex inspired communication. PATMOS 2017: 1-8 - 2016
- [c21]Erwan Moreac, André Rossi, Johann Laurent, Pierre Bomel:
Crosstalk-aware link power model for Networks-on-Chip. DASIP 2016: 121-128 - [c20]Asma Benmessaoud Gabis, Marc Sevaux, Pierre Bomel, Mouloud Koudil, Karima Benatchba:
Heuristic Based Routing Algorithm for Network on Chip. MCSoC 2016: 39-45 - 2014
- [c19]Yaset Oliva, Emmanuel Casseau, Kevin J. M. Martin, Pierre Bomel, Jean-Philippe Diguet, Hervé Yviquel, Mickaël Raulet, Erwan Raffin, Laurent Morin:
Orcc's compa-backend demonstration. DASIP 2014: 1-2 - [c18]Pierre Bomel, Kevin J. M. Martin, Jean-Philippe Diguet:
Virtual Devices for Hot-Pluggable Processors. DSD 2014: 58-65 - 2013
- [c17]Pierre Bomel, Marc Sevaux:
Parallel Deadlock Detection and Recovery for Networks-on-Chip Dedicated to Diffused Computations. DSD 2013: 29-36 - [c16]Pierre Bomel, Kevin J. M. Martin, Jean-Philippe Diguet:
Virtual UARTs for Reconfigurable Multi-processor Architectures. IPDPS Workshops 2013: 252-259 - 2012
- [c15]Pierre Bomel, Dominique Blouin, Mickael Lanoe, Eric Senn:
Functional validation of AADL models via model transformation to SystemC with ATL. ACES-MB@MoDELS 2012: 13-18 - 2010
- [c14]Guy Gogniat, Jorgiano Vidal, Linfeng Ye, Jérémie Crenne, Sébastien Guillet, Florent de Lamotte, Jean-Philippe Diguet, Pierre Bomel:
Self-reconfigurable Embedded Systems: From Modeling to Implementation. ERSA 2010: 84-96 - [c13]Emmanuel Boutillon, Yangyang Tang, Cédric Marchand, Pierre Bomel:
Hardware Discrete Channel Emulator. HPCS 2010: 452-458
2000 – 2009
- 2009
- [c12]Pierre Bomel, Jérémie Crenne, Linfeng Ye, Jean-Philippe Diguet, Guy Gogniat:
Ultra-Fast Downloading of Partial Bitstreams through Ethernet. ARCS 2009: 72-83 - [c11]Jean-Philippe Diguet, Linfeng Ye, Yvan Eustache, Jérémie Crenne, Pierre Bomel, Guy Gogniat, Jorgiano Vidal, Florent de Lamotte:
Networked Self-adaptive Systems: An Opportunity for Configuring in the Large. ERSA 2009: 81-90 - 2008
- [j3]Rasmus Abildgren, Jean-Philippe Diguet, Pierre Bomel, Guy Gogniat, Peter Koch, Yannick Le Moullec:
A Priori Implementation Effort Estimation for Hardware Design Based on Independent Path Analysis. EURASIP J. Embed. Syst. 2008 (2008) - [c10]Pierre Bomel, Guy Gogniat, Jean-Philippe Diguet:
A Networked, Lightweight and Partially Reconfigurable Platform. ARC 2008: 314-319 - [c9]Pierre Bomel, Jean-Philippe Diguet, Guy Gogniat, Jérémie Crenne:
Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems. ISPDC 2008: 228-234 - 2007
- [j2]Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin:
Constrained algorithmic IP design for system-on-chip. Integr. 40(2): 94-105 (2007) - [i3]Pierre Bomel, Eric Martin, Emmanuel Boutillon:
Synchronization Processor Synthesis for Latency Insensitive Systems. CoRR abs/0710.4659 (2007) - 2006
- [j1]Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin:
A formal method for hardware IP design and integration under I/O and timing constraints. ACM Trans. Embed. Comput. Syst. 5(1): 29-53 (2006) - [i2]Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin:
High-level synthesis under I/O Timing and Memory constraints. CoRR abs/cs/0605143 (2006) - [i1]Gwenolé Corre, Philippe Coussy, Pierre Bomel, Eric Senn, Eric Martin:
Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI. CoRR abs/cs/0605146 (2006) - 2005
- [c8]Pierre Bomel, Eric Martin, Emmanuel Boutillon:
Synchronization Processor Synthesis for Latency Insensitive Systems. DATE 2005: 896-897 - [c7]Nabil Abdelli, Pierre Bomel, Emmanuel Casseau, Anne-Marie Fouilliart, Christophe Jégo, Philippe Kajfasz, Bertrand Le Gal, Nathalie Le Heno:
Hardware Virtual Components Compliant with Communication System Standards. DSD 2005: 88-95 - [c6]Pierre Bomel, Nabil Abdelli, Eric Martin, Anne-Marie Fouilliart, Emmanuel Boutillon, Philippe Kajfasz:
High-Level Synthesis in Latency Insensitive System Methodology. DSD 2005: 96-101 - [c5]Emmanuel Casseau, Bertrand Le Gal, Pierre Bomel, Christophe Jégo, Sylvain Huet, Eric Martin:
C-based rapid prototyping for digital signal processing. EUSIPCO 2005: 1-4 - [c4]Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin:
A more efficient and flexible DSP design flow from Matlab-Simulink [FFT algorithm example]. ICASSP (5) 2005: 61-64 - [c3]Philippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin:
High-level synthesis under I/O timing and memory constraints. ISCAS (1) 2005: 680-683 - [c2]Pierre Bomel, Nabil Abdelli, Eric Martin, Anne-Marie Fouilliart, Emmanuel Boutillon, Philippe Kajfasz:
DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context. SAMOS 2005: 424-433 - 2004
- [c1]Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin:
Memory accesses management during high level synthesis. CODES+ISSS 2004: 42-47
Coauthor Index
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