default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDMaurizio Palesi
Person information
- affiliation: University of Catania, Italy
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j75]Abhijit Das
, Maurizio Palesi, John Kim, Partha Pratim Pande:
Guest Editorial Chip and Package-Scale Communication-Aware Architectures for General-Purpose, Domain-Specific, and Quantum Computing Systems. IEEE J. Emerg. Sel. Topics Circuits Syst. 14(3): 349-353 (2024)- [j74]Abhijit Das, Maurizio Palesi, John Kim, Partha Pratim Pande:
Chip and Package-Scale Interconnects for General-Purpose, Domain-Specific, and Quantum Computing Systems - Overview, Challenges, and Opportunities. IEEE J. Emerg. Sel. Topics Circuits Syst. 14(3): 354-370 (2024) - [j73]Abhijit Das, Enrico Russo, Maurizio Palesi:
Multi-Objective Hardware-Mapping Co-Optimisation for Multi-DNN Workloads on Chiplet-Based Accelerators. IEEE Trans. Computers 73(8): 1883-1898 (2024) - [j72]Minghua Tang, Enrico Russo, Maurizio Palesi:
Correction to: The position-based compression techniques for DNN model. J. Supercomput. 80(1): 1365 (2024) - [c92]Davide Patti, Salvatore Monteleone, Enrico Russo, Maurizio Palesi, Vincenzo Catania:
A Novel Timechain-Level Approach to the Modeling of the Bitcoin Lightning Network. Blockchain 2024: 11-18 - [c91]Davide Patti, Salvatore Monteleone, Enrico Russo, Maurizio Palesi, Vincenzo Catania:
Abstracting Bitcoin Lightning Network Complexity with Ultraviolet. ICBC 2024: 528-530 - [c90]Enrico Russo, Francesco Giulio Blanco, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Vincenzo Catania:
Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning. ISCAS 2024: 1-5 - [c89]Marco Finocchiaro, Salvatore Monteleone, Enrico Russo, Maurizio Palesi, Davide Patti:
Lessons Learned on the Design of Cost-Effective and Highly Compatible Smart Gloves. MECO 2024: 1-8 - [c88]Elio Vinciguerra, Enrico Russo, Maurizio Palesi, Giuseppe Ascia, Hamaad Rafique:
Improving LSTM-based Indoor Positioning via Simulation-Augmented Geomagnetic Field Dataset. MOST 2024: 251-259 - [i7]Enrico Russo, Francesco Giulio Blanco, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Vincenzo Catania:
Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning. CoRR abs/2403.00766 (2024) - [i6]Francesco Giulio Blanco, Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania:
Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems. CoRR abs/2404.08950 (2024) - [i5]Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania:
Attention-Based Deep Reinforcement Learning for Qubit Allocation in Modular Quantum Architectures. CoRR abs/2406.11452 (2024) - 2023
- [j71]Grazia Veronica Aiosa, Maurizio Palesi, Francesca Sapuppo:
EXplainable AI for Decision Support to Obesity Comorbidities Diagnosis. IEEE Access 11: 107767-107782 (2023) - [j70]Enrico Russo, Maurizio Palesi, Davide Patti, Salvatore Monteleone, Giuseppe Ascia, Vincenzo Catania:
Multiobjective End-to-End Design Space Exploration of Parameterized DNN Accelerators. IEEE Internet Things J. 10(2): 1800-1812 (2023) - [j69]Minghua Tang, Enrico Russo, Maurizio Palesi:
The position-based compression techniques for DNN model. J. Supercomput. 79(15): 17445-17474 (2023) - [c87]Enrico Russo, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Salvatore Monteleone, Vincenzo Catania:
Memory-Aware DNN Algorithm-Hardware Mapping via Integer Linear Programming. CF 2023: 134-143 - [c86]Grazia Veronica Aiosa, Maurizio Palesi, Francesca Sapuppo, Maria Gabriella Xibilia:
Explainable AI-Based Clinical Decision Support System for Obesity Comorbidity Analysis. e-Science 2023: 1-6 - [c85]Maurizio Palesi, Enrico Russo, Abhijit Das, John Jose:
Wireless enabled Inter-Chiplet Communication in DNN Hardware Accelerators. IPDPS Workshops 2023: 477-483 - [c84]Eduard Alarcón, Sergi Abadal, Fabio Sebastiano, Masoud Babaie, Edoardo Charbon, Peter Haring Bolívar, Maurizio Palesi, Elena Blokhina, Dirk Leipold, Robert Bogdan Staszewski, Artur García-Sáez, Carmen G. Almudéver:
Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package. ISCAS 2023: 1-5 - [c83]Hamaad Rafique, Davide Patti, Maurizio Palesi, Vincenzo Catania:
m-BMC: Exploration of Magnetic Field Measurements for Indoor Positioning Using mini-Batch Magnetometer Calibration. MOST 2023: 55-61 - [i4]Eduard Alarcón, Sergi Abadal, Fabio Sebastiano, Masoud Babaie, Edoardo Charbon, Peter Haring Bolívar, Maurizio Palesi, Elena Blokhina, Dirk Leipold, Robert Bogdan Staszewski, Artur García-Sáez, Carmen G. Almudéver:
Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package. CoRR abs/2303.14008 (2023) - [i3]Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi, Leandro Fiorin, Serena Curzel, Luca Benini, Francesco Conti, Angelo Garofalo, Cristian Zambelli, Enrico Calore, Sebastiano Fabio Schifano, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Stefania Perri, Nicola Petra, Davide De Caro, Luciano Lavagno, Teodoro Urso, Valeria Cardellini, Gian Carlo Cardarilli, Robert Birke:
A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. CoRR abs/2306.15552 (2023) - [i2]Fabrizio Ferrandi, Serena Curzel, Leandro Fiorin, Daniele Ielmini, Cristina Silvano, Francesco Conti, Alessio Burrello, Francesco Barchi, Luca Benini, Luciano Lavagno, Teodoro Urso, Enrico Calore, Sebastiano Fabio Schifano, Cristian Zambelli, Maurizio Palesi, Giuseppe Ascia, Enrico Russo, Nicola Petra, Davide De Caro, Gennaro Di Meo, Valeria Cardellini, Salvatore Filippone, Francesco Lo Presti, Francesco Silvestri, Paolo Palazzari, Stefania Perri:
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures. CoRR abs/2311.17815 (2023) - 2022
- [j68]Abhijit Das, Abhishek Kumar, John Jose, Maurizio Palesi:
Revising NoC in Future Multicore-Based Consumer Electronics for Performance. IEEE Consumer Electron. Mag. 11(3): 79-86 (2022) - [j67]Chixiao Chen, Jieming Yin, Yarui Peng, Maurizio Palesi, Wenxu Cao, Letian Huang, Amit Kumar Singh, Haocong Zhi, Xiaohang Wang:
Design Challenges of Intrachiplet and Interchiplet Interconnection. IEEE Des. Test 39(6): 99-109 (2022) - [j66]Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Andrea Mineo, Giuseppe Ascia, Vincenzo Catania:
DNN Model Compression for IoT Domain-Specific Hardware Accelerators. IEEE Internet Things J. 9(9): 6650-6662 (2022) - [c82]Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Vincenzo Catania:
MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping. DATE 2022: 226-231 - [c81]Enrico Russo, Maurizio Palesi, Davide Patti, Habiba Lahdhiri, Salvatore Monteleone, Giuseppe Ascia, Vincenzo Catania:
Combined Application of Approximate Computing Techniques in DNN Hardware Accelerators. IPDPS Workshops 2022: 16-23 - [c80]Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Habiba Lahdhiri, Giuseppe Ascia, Vincenzo Catania:
Exploiting the Approximate Computing Paradigm with DNN Hardware Accelerators. MECO 2022: 1-4 - [c79]Giuliano Canzonieri, Salvatore Monteleone, Maurizio Palesi, Enrico Russo, Davide Patti:
Analyzing the Impact of DNN Hardware Accelerators-Oriented Compression Techniques on General-Purpose Low-End Boards. MobiWIS 2022: 143-155 - [i1]Abhijit Das, Enrico Russo, Maurizio Palesi:
Multi-Objective Hardware-Mapping Co-Optimisation for Multi-Tenant DNN Accelerators. CoRR abs/2210.14657 (2022) - 2021
- [j65]Nizar Dahir, Ammar Karkar, Maurizio Palesi, Terrence S. T. Mak, Alex Yakovlev:
Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach. Integr. 81: 342-353 (2021) - [j64]Abhijit Das, Abhishek Kumar, John Jose, Maurizio Palesi:
Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty. IEEE Trans. Computers 70(6): 892-905 (2021) - [j63]Siyuan Xiao, Xiaohang Wang, Maurizio Palesi, Amit Kumar Singh, Liang Wang, Terrence S. T. Mak:
On Performance Optimization and Quality Control for Approximate-Communication-Enabled Networks-on-Chip. IEEE Trans. Computers 70(11): 1817-1830 (2021) - [j62]Dipika Deb, John Jose, Maurizio Palesi:
COPE: Reducing Cache Pollution and Network Contention by Inter-tile Coordinated Prefetching in NoC-based MPSoCs. ACM Trans. Design Autom. Electr. Syst. 26(3): 17:1-17:31 (2021) - [c78]Haocong Zhi, Xianuo Xu, Weijian Han, Zhilin Gao, Xiaohang Wang, Maurizio Palesi, Amit Kumar Singh, Letian Huang:
A Methodology for Simulating Multi-chiplet Systems Using Open-source Simulators. NANOCOM 2021: 18:1-18:6 - [c77]Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Vincenzo Catania:
LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation. PerCom Workshops 2021: 161-166 - [e10]Maurizio Palesi, Antonino Tumeo, Georgios I. Goumas, Carmen G. Almudéver:
CF '21: Computing Frontiers Conference, Virtual Event, Italy, May 11-13, 2021. ACM 2021, ISBN 978-1-4503-8404-9 [contents] - 2020
- [j61]Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti:
Impact of Users' Beliefs in Text-Based Linguistic Interaction. IEEE Access 8: 46861-46867 (2020) - [j60]Fangyang Shen, Mei Yang, Maurizio Palesi:
Introduction to the special section on intelligent computing systems and their applications. Comput. Electr. Eng. 85: 106816 (2020) - [j59]Kun-Chih Chen, Masoumeh Ebrahimi, Maurizio Palesi, Tim Kogel:
Guest Editorial: Communication-Aware Designs and Methodologies for Reliable and Adaptable On-Chip AI SubSystems and Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 265-267 (2020) - [j58]Seyed Morteza Nabavinejad, Mohammad Baharloo, Kun-Chih Chen, Maurizio Palesi, Tim Kogel, Masoumeh Ebrahimi:
An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 268-282 (2020) - [j57]Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose, Valerio Mario Salerno:
Exploiting Data Resilience in Wireless Network-on-chip Architectures. ACM J. Emerg. Technol. Comput. Syst. 16(2): 21:1-21:27 (2020) - [j56]Maurizio Palesi, Kun-Chih Jimmy Chen, Midia Reshadi:
Special issue on energy-efficient many-core embedded systems and architectures (SI: NoCArc18). J. Syst. Archit. 109: 101822 (2020) - [j55]Alireza Monemi, Farshad Khunjush, Maurizio Palesi, Hamid Sarbazi-Azad:
An Enhanced Dynamic Weighted Incremental Technique for QoS Support in NoC. ACM Trans. Parallel Comput. 7(2): 9:1-9:31 (2020) - [c76]Sirine Mnejja, Yassine Aydi, Mohamed Abid, Salvatore Monteleone, Maurizio Palesi, Davide Patti:
Implementing On-Chip Wireless Communication in Multi-stage Interconnection NoCs. AINA 2020: 533-546 - [c75]Andrea Mineo, Maurizio Palesi, Davide Patti, Vincenzo Catania:
Cloud-Based Energy Efficient Scheme for Sigfox Monarch as Asset Tracking Service. COINS 2020: 1-6 - [c74]Jordane Lorandel, Habiba Lahdhiri, Emmanuelle Bourdel, Salvatore Monteleone, Maurizio Palesi:
Efficient Compression Technique for NoC-based Deep Neural Network Accelerators. DSD 2020: 174-179 - [c73]Habiba Lahdhiri, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Jordane Lorandel, Emmanuelle Bourdel, Vincenzo Catania:
DNNZip: Selective Layers Compression Technique in Deep Neural Network Accelerators. DSD 2020: 526-533 - [c72]Giuseppe Ascia, Vincenzo Catania, John Jose, Salvatore Monteleone, Maurizio Palesi, Davide Patti:
Improving Inference Latency and Energy of Network-on-Chip based Convolutional Neural Networks through Weights Compression. IPDPS Workshops 2020: 54-63 - [c71]Abhijit Das, Abhishek Kumar, John Jose, Maurizio Palesi:
Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip Multi-processors. ISVLSI 2020: 147-152 - [c70]Giuseppe Ascia, Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti:
Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression. NOCS 2020: 1-6 - [e9]Maurizio Palesi, Gianluca Palermo, Catherine Graves, Eishi Arima:
Proceedings of the 17th ACM International Conference on Computing Frontiers, CF 2020, Catania, Sicily, Italy, May 11-13, 2020. ACM 2020, ISBN 978-1-4503-7956-4 [contents]
2010 – 2019
- 2019
- [j54]Dipika Deb, John Jose, Maurizio Palesi:
ECAP: energy-efficient caching for prefetch blocks in tiled chip multiprocessors. IET Comput. Digit. Tech. 13(6): 417-428 (2019) - [c69]Siyuan Xiao, Xiaohang Wang, Maurizio Palesi, Amit Kumar Singh, Terrence S. T. Mak:
ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-Chip. DATE 2019: 630-633 - [c68]Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose:
Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices. IoTSMS 2019: 227-234 - [c67]Minghua Tang, Maurizio Palesi:
Study on logic-based routing for 3D NOCs. NoCArc@MICRO 2019: 12:1-12:6 - [c66]Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose:
Analyzing networks-on-chip based deep neural networks. NOCS 2019: 23:1-23:2 - [c65]Dipika Deb, John Jose, Maurizio Palesi:
Performance Enhancement of Caches in TCMPs Using Near Vicinity Prefetcher. VLSID 2019: 13-18 - 2018
- [j53]Sarzamin Khan, Sheraz Anjum, Usman Ali Gulzari, Farruh Ishmanov, Maurizio Palesi, Muhammad Khalil Afzal:
An optimized hybrid algorithm in term of energy and performance for mapping real time workloads on 2d based on-chip networks. Appl. Intell. 48(12): 4792-4804 (2018) - [j52]Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti:
Improving Energy Efficiency in Wireless Network-on-Chip Architectures. ACM J. Emerg. Technol. Comput. Syst. 14(1): 9:1-9:24 (2018) - [j51]Minghua Tang, Jing Lin, Maurizio Palesi:
The Suboptimal Routing Algorithm for 2D Mesh Network. IEEE Trans. Computers 67(5): 704-716 (2018) - [c64]Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose:
Approximate Wireless Networks-on-Chip. DCIS 2018: 1-6 - [c63]Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose:
Improving energy consumption of NoC based architectures through approximate communication. MECO 2018: 1-4 - [c62]Abhijit Das, Sarath Babu, John Jose, Sangeetha Jose, Maurizio Palesi:
Critical Packet Prioritisation by Slack-Aware Re-Routing in On-Chip Networks. NOCS 2018: 12:1-12:8 - [c61]Salvatore Michele Biondi, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti:
smARTworks: A Multi-sided Context-aware Platform for the Smart Museum. PECCS 2018: 241-247 - [c60]Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti:
Packetization of Shared-Memory Traces for Message Passing Oriented NoC Simulation. ISC 2018: 311-325 - [c59]Simi Zerine Sleeba, John Jose, Maurizio Palesi, Rekha K. James, Maniyelil Govindankutty Mini:
Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip. VLSI-SoC 2018: 25-30 - 2017
- [j50]Alireza Monemi, Jia Wei Tang, Maurizio Palesi, Muhammad N. Marsono:
ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform. Microprocess. Microsystems 54: 60-74 (2017) - [j49]Alireza Monemi, Chia Yee Ooi, Maurizio Palesi, Muhammad N. Marsono:
Ping-lock round robin arbiter. Microelectron. J. 63: 81-93 (2017) - [j48]Minghua Tang, Xiaola Lin, Maurizio Palesi:
The Repetitive Turn Model for Adaptive Routing. IEEE Trans. Computers 66(1): 138-146 (2017) - [c58]Erwan Moreac, Johann Laurent, Pierre Bomel, André Rossi, Emmanuel Boutillon, Maurizio Palesi:
Energy aware Networks-on-Chip cortex inspired communication. PATMOS 2017: 1-8 - 2016
- [j47]Maurizio Palesi, Mario Collotta, Masoud Daneshtalab, Pradip Bose:
Special issue on energy efficient methods and systems in the emerging cloud era. J. Comput. Syst. Sci. 82(2): 173 (2016) - [j46]Mohamed Bakhouya, Masoud Daneshtalab, Maurizio Palesi, Hassan Ghasemzadeh:
Many-core System-on-Chip: architectures and applications. Microprocess. Microsystems 43: 1-3 (2016) - [j45]Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania:
Exploiting antenna directivity in wireless NoC architectures. Microprocess. Microsystems 43: 59-66 (2016) - [j44]Fangyang Shen, Maurizio Palesi, Mei Yang:
Introduction to the special section on "Sustainable processor architectures and applications". Microprocess. Microsystems 46: 105-106 (2016) - [j43]Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Partha Pratim Pande, Vincenzo Catania:
On-Chip Communication Energy Reduction Through Reliability Aware Adaptive Voltage Swing Scaling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(11): 1769-1782 (2016) - [j42]Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti:
Cycle-Accurate Network on Chip Simulation with Noxim. ACM Trans. Model. Comput. Simul. 27(1): 4 (2016) - [j41]Minghua Tang, Xiaola Lin, Maurizio Palesi:
Local Congestion Avoidance in Network-on-Chip. IEEE Trans. Parallel Distributed Syst. 27(7): 2062-2073 (2016) - [j40]Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania:
Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1535-1545 (2016) - [c57]Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti:
Improving the energy efficiency of wireless Network on Chip architectures through online selective buffers and receivers shutdown. CCNC 2016: 668-673 - [c56]Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti:
Energy efficient transceiver in wireless Network on Chip architectures. DATE 2016: 1321-1326 - [c55]Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono, Maurizio Palesi:
Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC. NoCArc@MICRO 2016: 9-14 - [c54]Amin Rezaei, Masoud Daneshtalab, Maurizio Palesi, Danella Zhao:
Efficient Congestion-Aware Scheme for Wireless on-Chip Networks. PDP 2016: 742-749 - 2015
- [j39]Fangyang Shen, Lingjia Liu, Maurizio Palesi:
Introduction to the special issue on "Emerging research in Internet of Things". Comput. Electr. Eng. 44: 104-106 (2015) - [j38]Masoud Daneshtalab, Maurizio Palesi, Terrence S. T. Mak:
Introduction to the special issue on NoC-based many-core architectures. Comput. Electr. Eng. 45: 359-361 (2015) - [j37]Maurizio Palesi, Davide Patti, Giuseppe Ascia, Daniela Panno, Vincenzo Catania:
Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip. J. Comput. Sci. 11(3): 552-566 (2015) - [j36]Minghua Tang, Xiaola Lin, Maurizio Palesi:
An Offline Method for Designing Adaptive Routing Based on Pressure Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(2): 307-320 (2015) - [j35]Nima Jafarzadeh, Maurizio Palesi, Saeedeh Eskandari, Shaahin Hessabi, Ali Afzali-Kusha:
Low Energy yet Reliable Data Communication Scheme for Network-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12): 1892-1904 (2015) - [j34]Minghua Tang, Xiaola Lin, Maurizio Palesi:
Routing Pressure: A Channel-Related and Traffic-Aware Metric of Routing Algorithm. IEEE Trans. Parallel Distributed Syst. 26(3): 891-901 (2015) - [c53]Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti:
Noxim: An open, extensible and cycle-accurate network on chip simulator. ASAP 2015: 162-163 - [c52]Andrea Mineo, Mohd Shahrizal Rusli, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono:
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures. DATE 2015: 513-518 - [c51]Hyunok Oh, Muhammad Shafique, Todor P. Stefanov, Maurizio Palesi:
Message from the Chairs. ESTIMedia 2015: 1 - [e8]Masoumeh Ebrahimi, Diana Goehringer, Masoud Daneshtalab, Maurizio Palesi, Sören Sonntag, Federico Angiolini:
Proceedings of the 3rd International Workshop on Many-core Embedded Systems (MES'2015) held on June 13, 2015 in conjunction with the 42nd International Symposium on Computer Architecture (ISCA'2015), Portland, OR, USA. ACM 2015, ISBN 978-1-4503-3408-2 [contents] - 2014
- [j33]Masoud Daneshtalab, Maurizio Palesi, Terrence S. T. Mak:
Introduction to the Special Issue on Network-on-Chip Architectures. Comput. Electr. Eng. 40(8): 257-259 (2014) - [j32]Masoud Daneshtalab, Maurizio Palesi, Juha Plosila, Ahmed Hemani:
Special issue on many-core embedded systems. Microprocess. Microsystems 38(6): 525 (2014) - [j31]Xiaohang Wang, Mei Yang, Yingtao Jiang, Peng Liu, Masoud Daneshtalab, Maurizio Palesi, Terrence S. T. Mak:
On self-tuning networks-on-chip for dynamic network-flow dominance adaptation. ACM Trans. Embed. Comput. Syst. 13(2s): 73:1-73:21 (2014) - [j30]Masoud Daneshtalab, Maurizio Palesi, Juha Plosila:
Editorial: Special issue on design challenges for many-core processors. ACM Trans. Embed. Comput. Syst. 13(3s): 100:1-100:2 (2014) - [j29]Maurizio Palesi, Todor P. Stefanov:
Editorial: Special Section on ESTIMedia'13. ACM Trans. Embed. Comput. Syst. 13(3s): 110:1 (2014) - [j28]Nima Jafarzadeh, Maurizio Palesi, Ahmad Khademzadeh, Ali Afzali-Kusha:
Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 675-685 (2014) - [c50]Davide Patti, Maurizio Palesi, Vincenzo Catania:
Merging Compilation and Microarchitectural Configuration Spaces for Performance/Power Optimization in VLIW-Based Systems. CSOC 2014: 203-212 - [c49]Mohammad Fattah, Maurizio Palesi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems. DAC 2014: 101:1-101:6 - [c48]Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania:
An adaptive transmitting power technique for energy efficient mm-wave wireless NoCs. DATE 2014: 1-6 - [c47]Xiaohang Wang, Baoxin Zhao, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Maurizio Palesi:
Adaptive power allocation for many-core systems inspired from multiagent auction model. DATE 2014: 1-4 - [c46]Mohd Shahrizal Rusli, Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono:
A Closed Loop Control based Power Manager for WiNoC Architectures. MES 2014: 60-63 - [e7]Masoud Daneshtalab, Masoumeh Ebrahimi, Maurizio Palesi, Federico Angiolini, Juha Plosila:
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, MES'2014, in conjunction with the 41st International Symposium on Computer Architecture, ISCA'2014, Minneapolis, MN, USA, June 15, 2014. ACM 2014, ISBN 978-1-4503-2822-7 [contents] - 2013
- [j27]Xiaohang Wang, Peng Liu, Mei Yang, Maurizio Palesi, Yingtao Jiang, Michael C. Huang:
Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip. J. Comput. Sci. Technol. 28(1): 54-71 (2013) - [j26]Xiaohang Wang, Mei Yang, Yingtao Jiang, Maurizio Palesi, Peng Liu, Terrence S. T. Mak, Nader Bagherzadeh:
Efficient multicast schemes for 3-D Networks-on-Chip. J. Syst. Archit. 59(9): 693-708 (2013) - [j25]Fangyang Shen, Mei Yang, Maurizio Palesi:
Guest Editors' Introduction to the Special Issue on "Novel On-Chip Parallel Architectures and Software Support". Parallel Comput. 39(9): 355-356 (2013) - [j24]Jian-Jia Chen, Maurizio Palesi:
Introduction to the special section on ESTIMedia'12. ACM Trans. Embed. Comput. Syst. 12(1s): 32:1-32:2 (2013) - [j23]José Flich Cardo, Maurizio Palesi:
Introduction to the special section on on-chip and off-chip network architectures. ACM Trans. Embed. Comput. Syst. 12(4): 104:1-104:2 (2013) - [c45]Giuseppe Ascia, Maurizio Palesi, Vincenzo Catania:
An Adaptive Output Selection Function Based on a Fuzzy Rule Base System for Network on Chip. DSD 2013: 505-512 - [c44]Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania:
Runtime Online Links Voltage Scaling for Low Energy Networks on Chip. DSD 2013: 941-944 - [c43]Todor P. Stefanov, Maurizio Palesi, Jian-Jia Chen, Jörg Henkel:
Message from the chairs. ESTIMedia 2013: 1 - [c42]Andrea Mineo, Marina Masi, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania:
Low Energy Mapping Techniques under Reliability and Bandwidth Constraints. HPCC/EUC 2013: 2088-2095 - [c41]Xiaohang Wang, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Maurizio Palesi:
On self-tuning networks-on-chip for dynamic network-flow dominance adaptation. NOCS 2013: 1-8 - [c40]Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania:
NoC links energy reduction through link voltage scaling. ICSAMOS 2013: 113-120 - [e6]Masoud Daneshtalab, Ahmed Hemani, Maurizio Palesi:
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, MES'2013, Held in conjunction with the 40th Annual IEEE/ACM International Symposium on Computer Architecture, ISCA 2013, June 24, 2013. ACM 2013, ISBN 978-1-4503-2063-4 [contents] - [e5]Maurizio Palesi, Terrence S. T. Mak, Masoud Daneshtalab:
Network on Chip Architectures, NoCArc '13, in conjunction with the 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 7, 2013. ACM 2013, ISBN 978-1-4503-2370-3 [contents] - 2012
- [j22]Rafael Tornero, Maurizio Palesi, José Duato:
A Topology-Independent Mapping Technique for Application-Specific Networks-on-Chip. Comput. Informatics 31(5): 939-970 (2012) - [j21]Fangyang Shen, Mei Yang, Maurizio Palesi:
Guest Editors' Introduction to the Special Issue on "Emerging Computing Architectures and Systems". Comput. Electr. Eng. 38(3): 722-723 (2012) - [j20]Maurizio Palesi, Rafael Tornero, Juan Manuel Orduña, Vincenzo Catania, Daniela Panno:
Designing Robust Routing Algorithms and Mapping Cores in Networks-on-Chip: A Multi-objective Evolutionary-based Approach. J. Univers. Comput. Sci. 18(7): 937-969 (2012) - [j19]Davide Patti, Andrea Spadaccini, Maurizio Palesi, Fabrizio Fazzino, Vincenzo Catania:
Supporting Undergraduate Computer Architecture Students Using a Visual MIPS64 CPU Simulator. IEEE Trans. Educ. 55(3): 406-411 (2012) - [j18]Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alex Yakovlev, Maurizio Palesi:
Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip. IEEE Trans. Parallel Distributed Syst. 23(7): 1205-1215 (2012) - [c39]Masoumeh Ebrahimi, Masoud Daneshtalab, Fahimeh Farahnakian, Juha Plosila, Pasi Liljeberg, Maurizio Palesi, Hannu Tenhunen:
HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks. NOCS 2012: 19-26 - [e4]Maurizio Palesi, Terrence S. T. Mak:
Fifth International Workshop on Network on Chip Architectures, NoCArc '12, Vancouver, BC, Canada, December 1, 2012. ACM 2012, ISBN 978-1-4503-1540-1 [contents] - 2011
- [j17]Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti:
Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems. Appl. Soft Comput. 11(1): 382-398 (2011) - [j16]Maurizio Palesi, Shashi Kumar, Radu Marculescu:
Network-on-chip architectures and design methodologies. Microprocess. Microsystems 35(2): 83-84 (2011) - [j15]Maurizio Palesi, Giuseppe Ascia, Fabrizio Fazzino, Vincenzo Catania:
Data Encoding Schemes in Networks on Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5): 774-786 (2011) - [c38]Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alexandre Yakovlev, Maurizio Palesi:
Run-time deadlock detection in networks-on-chip using coupled transitive closure networks. DATE 2011: 497-502 - [c37]Xiaohang Wang, Maurizio Palesi, Mei Yang, Yingtao Jiang, Michael C. Huang, Peng Liu:
Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip. NPC 2011: 232-247 - [c36]Xiaohang Wang, Maurizio Palesi, Mei Yang, Yingtao Jiang, Michael C. Huang, Peng Liu:
Low latency and energy efficient multicasting schemes for 3D NoC-based SoCs. VLSI-SoC 2011: 337-342 - [p1]Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania:
Application-Specific Routing Algorithms for Low Power Network on Chip Design. Low Power Networks-on-Chip 2011: 113-150 - [e3]Maurizio Palesi, Shashi Kumar:
4th International Workshop on Network on Chip Architectures, NoCArc '11, Porto Alegre, Brazil, December 4-5, 2011. ACM 2011, ISBN 978-1-4503-0947-9 [contents] - 2010
- [j14]Maurizio Palesi, Shashi Kumar, Vincenzo Catania:
Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 426-440 (2010) - [c35]Maurizio Palesi, Rickard Holsmark, Xiaohang Wang, Shashi Kumar, Mei Yang, Yingtao Jiang, Vincenzo Catania:
An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip. DSD 2010: 37-44 - [c34]Rickard Holsmark, Shashi Kumar, Maurizio Palesi:
A Multi-level Routing Scheme and Router Architecture to Support Hierarchical Routing in Large Network on Chip Platforms. Euro-Par Workshops 2010: 153-161 - [e2]Maurizio Palesi, Shashi Kumar, Zhonghai Lu, Ümit Y. Ogras:
Third International Workshop on Network on Chip Architectures, NoCArc'10, Atlanta, GA, USA, December 4, 2010. ACM 2010, ISBN 978-1-4503-0397-2 [contents]
2000 – 2009
- 2009
- [j13]Maurizio Palesi, Shashi Kumar, Vincenzo Catania:
Bandwidth-aware routing algorithms for networks-on-chip platforms. IET Comput. Digit. Tech. 3(5): 413-429 (2009) - [j12]Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania:
Application Specific Routing Algorithms for Networks on Chip. IEEE Trans. Parallel Distributed Syst. 20(3): 316-330 (2009) - [j11]Andres Mejia, Maurizio Palesi, José Flich, Shashi Kumar, Pedro López, Rickard Holsmark, José Duato:
Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs. IEEE Trans. Very Large Scale Integr. Syst. 17(3): 356-369 (2009) - [c33]Maurizio Palesi, Fabrizio Fazzino, Giuseppe Ascia, Vincenzo Catania:
Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. DSD 2009: 119-126 - [c32]Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Gianmarco De Francisci Morales:
An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures. DSD 2009: 643-650 - [c31]Rafael Tornero, Valentino Sterrantino, Maurizio Palesi, Juan M. Orduña:
A multi-objective strategy for concurrent mapping and routing in networks on chip. IPDPS 2009: 1-8 - [c30]Rickard Holsmark, Shashi Kumar, Maurizio Palesi, Andres Mejia:
HiRA: A methodology for deadlock free routing in hierarchical networks on chip. NOCS 2009: 2-11 - [e1]Maurizio Palesi, Shashi Kumar:
Second International Workshop on Network on Chip Architectures, NoCArc 2009, In conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42), December 12, 2009, New York, NY, USA. ACM 2009, ISBN 978-1-60558-774-5 [contents] - 2008
- [j10]Rickard Holsmark, Maurizio Palesi, Shashi Kumar:
Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions. J. Syst. Archit. 54(3-4): 427-440 (2008) - [j9]Vincenzo Catania, Maurizio Palesi, Davide Patti:
Reducing complexity of multiobjective design space exploration in VLIW-based embedded systems. ACM Trans. Archit. Code Optim. 5(2): 11:1-11:33 (2008) - [j8]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti:
Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip. IEEE Trans. Computers 57(6): 809-820 (2008) - [c29]Dario Frazzetta, Giuseppe Dimartino, Maurizio Palesi, Shashi Kumar, Vincenzo Catania:
Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. DSD 2008: 18-25 - [c28]Vincenzo Catania, Gianmarco De Francisci Morales, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti:
High Performance Computing for Embedded System Design: A Case Study. DSD 2008: 656-659 - [c27]Rafael Tornero, Juan M. Orduña, Maurizio Palesi, José Duato:
A Communication-Aware Topological Mapping Technique for NoCs. Euro-Par 2008: 910-919 - [c26]Maurizio Palesi, Giuseppe Longo, Salvatore Signorino, Rickard Holsmark, Shashi Kumar, Vincenzo Catania:
Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms. NOCS 2008: 97-106 - 2007
- [j7]Vincenzo Catania, Maurizio Palesi, Davide Patti:
Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-Objective Scenario. J. Circuits Syst. Comput. 16(5): 819-846 (2007) - [j6]Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti:
Efficient design space exploration for application specific systems-on-a-chip. J. Syst. Archit. 53(10): 733-750 (2007) - [j5]Davide Bertozzi, Shashi Kumar, Maurizio Palesi:
Networks-on-Chip: Emerging Research Topics and Novel Ideas. VLSI Design 2007: 26454:1-26454:3 (2007) - [c25]Alessandro G. Di Nuovo, Maurizio Palesi, Vincenzo Catania:
Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems. FUZZ-IEEE 2007: 1-6 - [c24]Maurizio Palesi, Shashi Kumar, Rickard Holsmark, Vincenzo Catania:
Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. IPDPS 2007: 1-8 - 2006
- [j4]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. J. Univers. Comput. Sci. 12(4): 370-394 (2006) - [c23]Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti:
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design. IEEE Congress on Evolutionary Computation 2006: 1736-1743 - [c22]Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania:
A methodology for design of application specific deadlock-free routing algorithms for NoC systems. CODES+ISSS 2006: 142-147 - [c21]Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania:
Fuzzy decision making in embedded system design. CODES+ISSS 2006: 223-228 - [c20]Rickard Holsmark, Maurizio Palesi, Shashi Kumar:
Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. DSD 2006: 696-703 - [c19]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti:
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks. ESTIMedia 2006: 79-84 - [c18]Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti:
An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design. ICSAMOS 2006: 115-122 - [c17]Maurizio Palesi, Shashi Kumar, Rickard Holsmark:
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures. SAMOS 2006: 373-384 - [c16]Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti:
An Hybrid Soft Computing Approach for Automated Computer Design. STAIRS 2006: 84-95 - 2005
- [j3]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 635-645 (2005) - [c15]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti:
Exploring Design Space of VLIW Architectures. ASAP 2005: 86-91 - [c14]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti:
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. ASP-DAC 2005: 940-943 - [c13]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
An evolutionary approach to network-on-chip mapping problem. Congress on Evolutionary Computation 2005: 112-119 - [c12]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti:
Hyperblock formation: a power/energy perspective for high performance VLIW architectures. ISCAS (4) 2005: 4090-4093 - 2004
- [j2]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
A GA-based design space exploration framework for parameterized system-on-a-chip platforms. IEEE Trans. Evol. Comput. 8(4): 329-346 (2004) - [c11]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
Multi-objective mapping for mesh-based NoC architectures. CODES+ISSS 2004: 182-187 - [c10]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti:
Multi-objective Optimization of a Parameterized VLIW Architecture. Evolvable Hardware 2004: 191-198 - 2003
- [c9]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato:
An evolutionary approach for reducing the switching activity in address buses. IEEE Congress on Evolutionary Computation 2003: 107-114 - [c8]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti:
EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration. ESTIMedia 2003: 65-72 - [c7]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato:
An evolutionary approach for reducing the energy in address buses. ISICT 2003: 76-81 - [c6]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems. PATMOS 2003: 21-30 - [c5]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
A Genetic Approach To Bus Encoding. VLSI-SOC 2003: 426-431 - 2002
- [c4]Maurizio Palesi, Tony Givargis:
Multi-objective design space exploration using genetic algorithms. CODES 2002: 67-72 - [c3]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
A Framework for Design Space Exploration of Parameterized VLSI Systems. ASP-DAC/VLSI Design 2002: 245-250 - 2001
- [j1]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Sarta:
An Instruction-Level Power Analysis Model with Data Dependency. VLSI Design 12(2): 245-273 (2001) - [c2]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
Parameterised system design based on genetic algorithms. CODES 2001: 177-182 - [c1]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms. VLSI-SOC 2001: 157-168
Coauthor Index
[c90] [c88] [i7] [i6] [i5] [j70] [c87] [i3] [i2] [j66] [c82] [c81] [c80] [c77] [j57] [c73] [c72] [c70] [c68] [c66] [c64] [c63] [j45] [j43] [j40] [j37] [c52] [c48] [c46] [c45] [c44] [c42] [c40] [j17] [j15] [c33] [j8] [j6] [j4] [c23] [c21] [c19] [c18] [j3] [c15] [c14] [c13] [c12] [j2] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c3] [j1] [c2] [c1]
[c92] [c91] [c90] [i7] [i6] [i5] [j70] [c87] [c83] [j66] [c82] [c81] [c80] [c77] [j61] [j57] [c75] [c73] [c72] [c70] [c68] [c66] [j52] [c64] [c63] [c61] [c60] [j45] [j43] [j42] [j40] [c57] [c56] [j37] [c53] [c52] [c50] [c48] [c46] [c45] [c44] [c42] [c40] [j20] [j19] [j17] [j15] [p1] [j14] [c35] [j13] [j12] [c33] [c32] [j9] [j8] [c29] [c28] [c26] [j7] [j6] [c25] [c24] [j4] [c23] [c22] [c21] [c19] [c18] [j3] [c15] [c14] [c13] [c12] [j2] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c3] [j1] [c2] [c1]
[c92] [c91] [c90] [c89] [i7] [i6] [i5] [j70] [c87] [c83] [i3] [j66] [c82] [c81] [c80] [c79] [c77] [j61] [j57] [c76] [c75] [c73] [c72] [c70] [c68] [c66] [j52] [c64] [c63] [c61] [c60] [j42] [c57] [c56] [j37] [c53] [c50] [j19] [j17] [c32] [j9] [j8] [c28] [j7] [j6] [c23] [c21] [c19] [c18] [c16] [c15] [c14] [c12] [c10] [c8]
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-17 20:32 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
