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ORCIDV. Bharath Sreenivasulu
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2020 – today
- 2024
[j6]V. Bharath Sreenivasulu
, Aruna Kumari Neelam, Asisa Kumar Panigrahy, Lokesh Vakkalakula, Jawar Singh, Shiv Govind Singh:
Benchmarking of Multi-Bridge-Channel FETs Toward Analog and Mixed-Mode Circuit Applications. IEEE Access 12: 7531-7539 (2024)- [j5]Aruna Kumari Neelam, V. Bharath Sreenivasulu, Vikas Vijayvargiya, Abhishek Kumar Upadhyay, J. Ajayan, M. Uma:
Performance Comparison of Nanosheet FET, CombFET, and TreeFET: Device and Circuit Perspective. IEEE Access 12: 9563-9571 (2024) - [j4]Asisa Kumar Panigrahy, Veera Venkata Sai Amudalapalli, Depuru Shobha Rani, Muralidhar Nayak Bhukya, Hima Bindu Valiveti, V. Bharath Sreenivasulu, Raghunandan Swain:
Spacer Dielectric Analysis of Multi-Channel Nanosheet FET for Nanoscale Applications. IEEE Access 12: 73160-73168 (2024) - 2023
- [j3]V. Bharath Sreenivasulu, Aruna Kumari Neelam, Sekhar Reddy Kola, Jawar Singh, Yiming Li:
Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison. IEEE Access 11: 90421-90429 (2023) - [j2]B. Mounika, J. Ajayan, Sandip Bhattacharya, D. Nirmal, V. Bharath Sreenivasulu, N. Aruna Kumari:
Investigation on effect of AlN barrier thickness and lateral scalability of Fe-doped recessed T-gate AlN/GaN/SiC HEMT with polarization-graded back barrier for future RF electronic applications. Microelectron. J. 140: 105923 (2023) - 2022
- [c1]Aruru Sai Kumar, M. Deekshana, V. Bharath Sreenivasulu, Rajendra Prasad Somineni, D. Kanthi Sudha:
Characterization for Sub-5nm Technology Nodes of Junctionless Gate-All-Around Nanowire FETs. ICCCNT 2022: 1-5 - 2021
- [j1]V. Bharath Sreenivasulu, Vadthiya Narendar:
Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes. Microelectron. J. 116: 105214 (2021)
Coauthor Index
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