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ORCIDSagar S. Sabade
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2000 – 2009
- 2006
[j5]Sagar S. Sabade, D. M. H. Walker:
Estimation of fault-free leakage current using wafer-level spatial information. IEEE Trans. Very Large Scale Integr. Syst. 14(1): 91-94 (2006)- 2005
- [j4]Sagar S. Sabade, Duncan M. Hank Walker:
IC Outlier Identification Using Multiple Test Metrics. IEEE Des. Test Comput. 22(6): 586-595 (2005) - 2004
- [j3]Sagar S. Sabade, D. M. H. Walker:
IDDQ data analysis using neighbor current ratios. J. Syst. Archit. 50(5): 287-294 (2004) - [j2]Sagar S. Sabade, D. M. H. Walker:
IDDX-based test methods: A survey. ACM Trans. Design Autom. Electr. Syst. 9(2): 159-198 (2004) - [c9]Sagar S. Sabade, D. M. H. Walker:
Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests. VLSI Design 2004: 889-894 - [c8]Sagar S. Sabade, D. M. H. Walker:
On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set. VTS 2004: 65-72 - 2003
- [c7]Sagar S. Sabade, D. M. H. Walker:
CROWNE: Current Ratio Outliers with Neighbor Estimator. DFT 2003: 132-139 - [c6]Sagar S. Sabade, D. M. H. Walker:
Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification. VLSI Design 2003: 361- - [c5]Sagar S. Sabade, D. M. H. Walker:
Use of Multiple IDDQ Test Metrics for Outlier Identification. VTS 2003: 31-38 - 2002
- [j1]Sagar S. Sabade, D. M. H. Walker:
IDDQ Test: Will It Survive the DSM Challenge? IEEE Des. Test Comput. 19(5): 8-16 (2002) - [c4]Sagar S. Sabade, D. M. H. Walker:
Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis. DFT 2002: 381-389 - [c3]Sagar S. Sabade, D. M. H. Walker:
Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. ASP-DAC/VLSI Design 2002: 755-760 - [c2]Sagar S. Sabade, D. M. H. Walker:
Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction. VTS 2002: 81-86 - 2001
- [c1]Sagar S. Sabade, D. M. H. Walker:
Improved wafer-level spatial analysis for I_DDQ limit setting. ITC 2001: 82-91
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