default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID16th VLSI Design 2003: New Delhi, India
- 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India. IEEE Computer Society 2003, ISBN 0-7695-1868-0
Keynote Speeches
- Gene A. Frantz:
Personal and Portable: The Evolving Definition. 3 - Ted Vucurevich:
Living at the Edge. 4 - Rajeev Madhavan:
India-Building the Tall, Thin VLSI Engineer. 5 - A. Vasudevan:
Advances in VLSI Design and Product Development Challenges. 6
Tutorials
- Sandeep K. Shukla, Jean-Pierre Talpin, Stephen A. Edwards, Rajesh K. Gupta:
High Level Modeling and Validation Methodologies for Embedded Systems: Bridging the Productivity Gap. 9-14 - Rajiv V. Joshi, Kaushik Roy:
Design of Deep Sub-Micron CMOS Circuits. 15-16 - Rubin A. Parekhji:
Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions. 17 - Ramesh Chandra, Preeti Ranjan Panda, Jörg Henkel, Sri Parameswaran
, Loganath Ramachandran:
Specification and Design of Multi-Million Gate SOCs. 18-19 - Natarajan Mahadeva Iyer, M. K. Radhakrishnan:
ESD Reliability Challenges for RF/Mixed Signal Design & Processing. 20-21 - Krithi Ramamritham, Kavi Arya:
System Support for Embedded Applications. 22-
Analog and RF Devices
- Anantha Nag, K. Radhakrishna Rao:
Narrow Band Noise Suppression Scheme for improving Signal to Noise Ratio. 25-29 - Sounil Biswas, Baquer Mazhari:
A Path Sensitization Technique for Testing of Switched Capacitor Circuits. 30-35 - Prashant Admane, Manoj Patasani, Biju Viswanathan:
A Novel RF Front-End Chipset For ISM Band Wireless Applications. 36-41 - Saikat Sarkar, Padmanava Sen, Arvind Raghava, Sudipto Chakarborty, Joy Laskar:
Development of 2.4 GHz RF Transceiver Front-end Chipset in 0.25µm CMOS. 42-
Physical Design
- Muthukumar Venkatesan, Henry Selvaraj:
Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation. 51-57 - Cristinel Ababei, Kia Bazargan:
Timing Minimization by Statistical Timing hMetis-based Partitioning. 58-63 - Sachin B. Patkar, H. Narayanan:
An Efficient Practical Heuristic For Good Ratio-Cut Partitioning. 64-69 - Jong-Sheng Cherng, Sao-Jie Chen:
An Efficient Multi-Level Partitioning Algorithm for VLSI Circuits. 70-
FPGA
- Rohit Pandey, Santanu Chattopadhyay:
Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach". 79-84 - Zhibin Dai, Dilip K. Banerji:
Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy. 85-90 - Manish Handa, Rajesh Radhakrishnan, Madhubanti Mukherjee, Ranga Vemuri:
A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs. 91-
MOS Technology
- Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao:
Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics. 99-104 - R. Srinivasan, Navakanta Bhat:
Effect of Scaling on the Non-quasi-static Behaviour of the MOSFET for RF IC's. 105-109 - Najeeb-ud-Din Hakim, V. Ramgopal Rao, J. Vasi:
Small Signal Characteristics of Thin Film Single Halo SOI MOSFET for Mixed Mode Applications. 110-115 - Manisha Pattanaik, Swapna Banerjee:
A New Approach to Analyze a Sub-micron CMOS Inverter. 116-121 - Vinod Menezes, C. B. Keshav, Sushil Gupta, M. Roopashree, S. Krishnan, A. Amerasekera, G. Palau:
Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node. 122-127 - D. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao:
Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits. 128-
ATPG and DFT
- Arun Krishnamachary, Jacob A. Abraham:
Effects of Multi-cycle Sensitization on Delay Tests. 137-142 - Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja:
Exclusive Test and its Applications to Fault Diagnosis. 143-148 - Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell:
A Fault-Independent Transitive Closure Algorithm for Redundancy Identification. 149-154 - Samir Roy, Ujjwal Maulik, Biplab K. Sikdar:
Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines. 155-160 - Sukanta Das, Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri:
Design Of A Universal BIST (UBIST) Structure. 161-166 - Petros Drineas, Yiorgos Makris:
SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs. 167-
VLSI Processors
- Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar:
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks. 177-182 - Vadali Srinivasa Murty, P. C. Reghu Raj, S. Raman:
Design of a high speed string matching co-processor for NLP. 183-188 - Partha S. Roop, Zoran A. Salcic, Morteza Biglari-Abhari, Abbas Bigdeli:
A New Reactive Processor with Architectural Support for Control Dominated Embedded Systems. 189-194 - Kyriakos Vlachos, Nikos A. Nikolaou, Theofanis Orphanoudakis, Stylianos Perissakis, Dionisios N. Pnevmatikatos, George Kornaros, J. A. Sanchez, George E. Konstantoulakis:
Processing and Scheduling Components in an Innovative Network Processor Architecture. 195-201 - Srikar Movva, S. Srinivasan:
A Novel Architecture for Lifting-Based Discrete Wavelet Transform for JPEG2000 Standard suitable for VLSI. 202-207 - Bipul Das, Swapna Banerjee:
A Memory Efficient 3-D DWT Architecture. 208-
Memory Technology
- Mohammad Gh. Mohammad, Kewal K. Saluja:
Electrical Model For Program Disturb Faults in Non-Volatile Memories. 217-222 - S. Mahapatra, S. Shukuri, Jeff Bude:
Substrate Bias Effect on Cycling Induced Performance Degradation of Flash EEPROMs. 223-226 - Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jane Irwin:
Analyzing Soft Errors in Leakage Optimized SRAM Design. 227-233 - Li Ding, Pinaki Mazumder:
The Impact of Bit-Line Coupling and Ground Bounce on CMOS SRAM Performance. 234-
Verification and Synthesis
- Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula:
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines. 243-248 - Pao-Ann Hsiung, Shu-Yu Cheng:
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems. 249-254 - Souvik Basu, Rajat Moona:
High Level Synthesis from Sim-nML Processor Models. 255-260 - Yong Sin Kim, Soo Hwan Kim, Kwang-Hyun Baek, Suki Kim, Sung-Mo Kang:
Multiple Trigonometric Approximation of Sine-Amplitude with Small ROM Size for Direct Digital Frequency Synthesizers. 261-
Security
- Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar:
Embedding Security in Wireless Embedded Systems. 269-270 - Subhayan Sen, Sk. Iqbal Hossain, Kabirul Islam, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri:
Cryptosystem Designed for Embedded System Security. 271-276 - Chandrama Shaw, Debashis Chatterji, Pradipta Maji, Subhayan Sen, B. N. Roy, Parimal Pal Chaudhuri:
A Pipeline Architecture for Encompression (Encryption + Compression) Technology. 277-282 - Annajirao Garimella, M. V. V. Satyanarayana, R. Satish Kumar, P. S. Murugesh, U. C. Niranjan:
VLSI Implementation of Online Digital Watermarking Technique with Difference Encoding for 8-Bit Gray Scale Images. 283-
Low-Power Technologies
- Koushik K. Das, Richard B. Brown:
Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology. 291-296 - Chandramouli Gopalakrishnan, Srinivas Katkoori:
Resource Allocation and Binding Approach for Low Leakage Power. 297-302 - Debasis Samanta, Ajit Pal:
Synthesis of Dual-VT Dynamic CMOS Circuits. 303-308 - J. Veerendra Kumar, K. Radhakrishna Rao:
A Low-Voltage Low Power CMOS Companding Filter. 309-314 - W. Kuang, J. S. Yuan:
An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital Design. 315-319 - Mahesh Mamidipaka, Nikil D. Dutt, Kamal S. Khouri:
A Methodology for Accurate Modeling of Energy Dissipation in Array Structures. 320-
Test Optimization
- Hideyuki Ichihara, Kozo Kinoshita, Koji Isodono, Shigeki Nishikawa:
Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs. 329-334 - Irith Pomeranz, Sudhakar M. Reddy:
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences. 335-340 - Santanu Chattopadhyay, K. Sudarsana Reddy:
Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips. 341-346 - C. P. Ravikumar, Nitin Kakkar, Saurabh Chopra:
Mutual Testing based on Wavelet Transforms. 347-352 - Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal:
New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. 353-360 - Sagar S. Sabade, D. M. H. Walker:
Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification. 361-
System-on-a-Chip
- Jiong Luo, Niraj K. Jha:
Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems. 369-375 - Thomas Wild, Jürgen Foag, Nuria Pazos, Winthir Brunnbauer:
Mapping and Scheduling for Architecture Exploration of Networking SoCs. 376-381 - Praveen Bhojwani, Rabi N. Mahapatra:
Interfacing Cores with On-chip Packet-Switched Networks. 382-387 - Robert H. Bell Jr., Lizy Kurian John:
Interface Design Techniques for Single-Chip Systems. 388-394 - Bedabrata Pain, Bruce Hancock, Thomas Cunningham, Guang Yang, Suresh Seshadri, Julie Heynssens, Chris Wrigley:
CMOS Digital Imager Design from a System-on-a-chip Perspective. 395-400 - Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar:
Extending Platform-Based Design to Network on Chip Systems. 401-
Coupling Effects
- Shabbir H. Batterywala, Narendra V. Shenoy:
A Method to Estimate Slew and Delay in Coupled Digital Circuits. 411-416 - Vani Prasad, Madhav P. Desai:
Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy. 417-422 - Zhongliang Pan:
Bridging Fault Detections for Testable Realizations of Logic Functions. 423-
Power Estimation and Control
- Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar:
Efficient RTL Power Estimation for Large Designs. 431-439 - Alberto García Ortiz, Tudor Murgan, Manfred Glesner:
Transition Activity Estimation for General Correlated Data Distributions. 440-445 - Saraju P. Mohanty, N. Ranganathan:
Energy Efficient Scheduling for Datapath Synthesis. 446-451 - Ashok K. Murugavel, N. Ranganathan:
A Game-Theoretic Approach for Binding in Behavioral Synthesis. 452-
High-Level Synthesis
- Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau:
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations. 461-466 - Weidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey:
High-level Synthesis of Multi-process Behavioral Descriptions. 467-473 - G. N. Mangalam, Sanjiv Narayan, Paul van Besouw, LaNae J. Avra, Anmol Mathur, Sanjeev Saluja:
Graph Transformations for Improved Tree Height Reduction. 474-479 - Keith S. Vallerio, Niraj K. Jha:
Task Graph Extraction for Embedded System Synthesis. 480-
Device Design
- Mamidala Jagadesh Kumar, D. Venkateshrao:
A New Lateral SiGe-Base PNM Schottky Collector Bipolar Transistor on SOI for Non-saturating VLSI Logic Design. 489-492 - Alejandro F. González, Pinaki Mazumder:
Comparison of Bistable Circuits Based on Resonant-Tunneling Diodes. 493-492 - Abhisek Dixit, V. Ramgopal Rao:
A Novel Dynamic Threshold Operation Using Electrically Induced Junction MOSFET in the Deep Sub-micrometer CMOS Regime. 499-503 - Qadeer Ahmad Khan, Sanjay Kumar Wadhwa, Kulbhushan Misri:
A Low Voltage Switched-Capacitor Current Reference Circuit with low dependence on Process, Voltage and Temperature. 504-506 - Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi, P. K. Ghosh:
Synthesis Of Programmable Current Mode Linear Analog Circuit. 507-512 - Geun Rae Cho, Tom Chen:
On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. 513-
Low-Power Design/Test
- Chi-Ming Tsai, Guang-Wan Liao, Rung-Bin Lin:
A Low Power-Delay Product Page-Based Address Bus Coding Method. 521-526 - Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. 527-532 - Ganesh Venkataraman, Sudhakar M. Reddy, Irith Pomeranz:
GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment. 533-538 - Saraju P. Mohanty, N. Ranganathan:
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis. 539-545 - Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang:
Low-Energy BIST Design for Scan-based Logic Circuits. 546-551 - Santanu Chattopadhyay, Naveen Choudhary:
Genetic Algorithm based Approach for Low Power Combinational Circuit Testing. 552-
Reconfigurable System Software
- Kiran Puttegowda, William Worek, Nicholas Pappas, Anusha Dandapani, Peter Athanas, Allan Dickerman:
A Run-Time Reconfigurable System for Gene-Sequence Searching. 561-566 - Wu Jigang, Thambipillai Srikanthan:
A Run-time Reconfiguration Algorithm for VLSI Arrays. 567-572 - T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar:
Optimal Code and Data Layout in Embedded Systems. 573-578 - Pao-Ann Hsiung, Feng-Shi Su:
Synthesis of Real-Time Embedded Software by Timed Quasi-Static Scheduling. 579-584 - Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar:
SoC Synthesis with Automatic Hardware Software Interface Generation. 585-
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-04 01:25 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
