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2020 – today
- 2022
[c6]Matthew M. Ziegler, Lakshmi N. Reddy, Robert L. Franch:
Design Flow Parameter Optimization with Multi-Phase Positive Nondeterministic Tuning. ISPD 2022: 29-37
2010 – 2019
- 2014
- [c5]Matthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert L. Franch, Wing K. Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban:
POWER8 design methodology innovations for improving productivity and reducing power. CICC 2014: 1-9 - 2012
- [c4]Liang-Teck Pang, Phillip J. Restle, Matthew R. Wordeman, Joel A. Silberman, Robert L. Franch, Gary W. Maier:
A shorted global clock design for multi-GHz 3D stacked chips. VLSIC 2012: 170-171
2000 – 2009
- 2008
- [c3]Robert L. Franch, Phillip J. Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, Gerard Salem:
On-chip Timing Uncertainty Measurements on IBM Microprocessors. ITC 2008: 1-7 - 2007
- [c2]Robert L. Franch, Phillip J. Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, Gerard Salem:
On-chip timing uncertainty measurements on IBM microprocessors. ITC 2007: 1-7 - 2003
- [j4]Mary Y. L. Wisniewski, Emmanuel Yashchin, Robert L. Franch, David P. Conrady, Giovanni Fiorenza, I. Cevdet Noyan:
Estimating the efficiency of collaborative problem-solving, with applications to chip design. IBM J. Res. Dev. 47(1): 77-88 (2003) - [j3]Mary Y. L. Wisniewski, Emmanuel Yashchin, Robert L. Franch, David P. Conrady, Daniel N. Maynard, Giovanni Fiorenza, I. Cevdet Noyan:
The physical design of on-chip interconnections. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 254-276 (2003)
1990 – 1999
- 1997
- [j2]Robert L. Franch, J. Ji, C. L. Chen:
A 640-ps, 0.25-μm CMOS, 16×64-b three-port register file. IEEE J. Solid State Circuits 32(8): 1288-1292 (1997) - 1992
- [c1]January Kister, Robert L. Franch:
Advances in Membrane Probe Technology. ITC 1992: 927-935
1980 – 1989
- 1988
- [j1]Barbara A. Chappell, Terry I. Chappell, Stanley E. Schuster, Hermann M. Segmuller, James W. Allan, Robert L. Franch, Phillip J. Restle:
Fast CMOS ECL receivers with 100-mV worst-case sensitivity. IEEE J. Solid State Circuits 23(1): 59-67 (1988)
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