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ORCIDZhicheng Dong 0002
Person information
- affiliation: Xidian University, Xi'an, China
Other persons with the same name
- Zhicheng Dong — disambiguation page
- Zhicheng Dong 0001
![[0000-0002-6606-0941]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-6606-0941")
— Shanghai University, School of Computer Engineering and Science, China - Zhicheng Dong 0003 — Tibet University, Lhasa, China
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2020 – today
- 2025
[j9]Yi Shen, Shubin Liu, Yue Cao, Haolin Han, Hongzhi Liang, Zhicheng Dong, Dengquan Li, Ruixue Ding, Zhangming Zhu:
A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage. IEEE J. Solid State Circuits 60(1): 260-271 (2025)- [j8]Zekai Yang, Xiaoteng Zhao, Huajin Sun, Xianting Su, Zhicheng Dong, Yilong Dong, Yukui Yu, Hongzhi Liang, Shubin Liu:
A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator. Microelectron. J. 166: 106870 (2025) - [j7]Zekai Yang, Xiaoteng Zhao, Huajin Sun, Xianting Su, Zhicheng Dong, Yilong Dong, Yukui Yu, Hongzhi Liang, Shubin Liu:
A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator. Microelectron. J. 166: 106872 (2025) - [j6]Miao Zhang, Ruidong Li, Xiaoteng Zhao, Xianting Su, Zhicheng Dong, Zekai Yang, Hongyu Su, Hongzhi Liang, Yukui Yu, Shubin Liu:
Load-driven inductive peaking design for broad band continuous-time linear equalizer. Microelectron. J. 166: 106873 (2025) - [j5]Jie Liu, Xianting Su, Zekai Yang, Zhicheng Dong, Chenxi Han, Xiaoteng Zhao, Shubin Liu:
A 7-bit 8 GHz phase interpolator with eight-phase output using a linear weighting scheme using only 50 % interpolation units. Microelectron. J. 166: 106874 (2025) - [j4]Zekai Yang, Xiaoteng Zhao, Huajin Sun, Xianting Su, Zhicheng Dong, Yilong Dong, Yukui Yu, Hongzhi Liang, Shubin Liu:
Withdrawal notice to "A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator" [Microelectron. J. 166 (2025) 106872]. Microelectron. J. 166: 106946 (2025) - [j3]Yuan Gao, Depeng Sun, Chao Gu, Feng Bu, Bowen Wang, Rong Zhou, Zhicheng Dong, Xiaoteng Zhao, Tao Zhang, Ruixue Ding, Shubin Liu, Zhangming Zhu:
A Low-Noise Class-F23 VCO With Harmonic Resonance Expansion and 2nd/3rd-Harmonic Outputs for Multiband mm-Wave Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 72(11): 6679-6690 (2025) - [j2]Linwei Wang, Rong Zhou, Jianhang Yang, Zhen Li, Zhicheng Dong, Shubin Liu, Zhangming Zhu:
A 0.4-V 500-kHz FLL With Reused TDA-Based Calibration and OTA-Accelerated Technique in 65-nm CMOS for Sleep Timer. IEEE Trans. Circuits Syst. II Express Briefs 72(1): 93-97 (2025) - [c6]Xiaoteng Zhao, Yuhao Zhang, Hao Chang, Yilong Dong, Chenxi Han, Zekai Yang, Zhicheng Dong, Rong Zhou, Shubin Liu, Zhangming Zhu:
A Reference-Less CDR Using SAR-Based Frequency-Acquisition Technique Achieving 55ns Constant Band-Searching Time and up to 63.64Gb/s/µs Acquisition Speed. ISSCC 2025: 150-152 - 2024
- [j1]Zhicheng Dong, Shubin Liu, Xiaoteng Zhao, Baotian Hao, Xianting Su, Hongzhi Liang, Menghao Wang, Zhangming Zhu:
A 0.08%/V 32.3-ppm/°C 36.6-kHz Unregulated Current-Reuse Ring Oscillator With VGS-Ratio-Based Compensation Using One-Type-Only Resistor. IEEE J. Solid State Circuits 59(11): 3767-3779 (2024) - [c5]Zhicheng Dong, Xiaoteng Zhao, Zekai Yang, Xianting Su, Haolin Han, Feng Bu, Rong Zhou, Depeng Sun, Yong Chen, Shubin Liu, Ruixue Ding, Zhangming Zhu:
A 0.0006-mm2 0.13-pJ/bit 9-21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1: 3 DEMUX in 65-nm CMOS. A-SSCC 2024: 1-3 - [c4]Miao Zhang, Xianting Su, Zekai Yang, Zhicheng Dong, Weitan Huang, Menghao Wang, Yukui Yu, Xiaoteng Zhao, Shubin Liu, Zhangming Zhu:
A 0.9-V Supply Up to 21.5-dB Boost Gain Analog Front-End with T-coilloaded CTLE and VGA in 28-nm CMOS for 112-Gb/s PAM-4 Medium-Reach Receivers. ICTA 2024: 172-173 - [c3]Zhicheng Dong, Xiaoteng Zhao, Weitan Huang, Yuan Gao, Depeng Sun, Shubin Liu, Lihong Yang, Zhangming Zhu:
A 30.5-to-31 GHz Sampling PLL With Double-Edge Sampling PD and Implict Common-Mode VCO Scoring 39.69-fs RMS Jitter and -253.6-dB FoM in a 0.047mm2 Area. ISCAS 2024: 1-5 - 2023
- [c2]Zhicheng Dong, Shubin Liu, Xiaoteng Zhao, Baotian Hao, Hongzhi Liang, Haolin Han, Menghao Wang, Weijie Han, Zhangming Zhu:
A 0.012mm2 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply. CICC 2023: 1-2 - [c1]Yi Shen, Shubin Liu, Yue Cao, Haolin Han, Hongzhi Liang, Zhicheng Dong, Dengquan Li, Ruixue Ding, Zhangming Zhu:
A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage. CICC 2023: 1-2
Coauthor Index
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