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ORCIDWai Shing Lau
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2010 – 2019
- 2012
[j7]Wai Shing Lau, Peizhen Yang, Soh Yun Siah, Lap Chan:
The role of a tensile stress bias for a sensitive silicon mechanical stress sensor based on a change in gate-induced-drain leakage current. Microelectron. Reliab. 52(11): 2847-2850 (2012)- 2010
- [j6]Wai Shing Lau, Peizhen Yang, Eng Hua Lim, Yee Ling Tang, Seow Wei Lai, V. L. Lo, Soh Yun Siah, Lap Chan:
Observation of halo implant from the drain side reaching the source side and vice versa in extremely short p-channel transistors. Microelectron. Reliab. 50(3): 346-350 (2010)
2000 – 2009
- 2009
- [j5]Wai Shing Lau, Peizhen Yang, Jason Zhiwei Chian, V. Ho, C. H. Loh, Soh Yun Siah, Lap Chan:
Drain current saturation at high drain voltage due to pinch off instead of velocity saturation in sub-100 nm metal-oxide-semiconductor transistors. Microelectron. Reliab. 49(1): 1-7 (2009) - 2008
- [j4]Wai Shing Lau, S. Gunawan, Joy B. H. Tan, B. P. Singh:
The application of polyimide/silicon nitride dual passivation to AlxGa1-xN/GaN high electron mobility transistors. Microelectron. Reliab. 48(2): 187-192 (2008) - [j3]Wai Shing Lau, Peizhen Yang, Chee Wee Eng, V. Ho, C. H. Loh, Soh Yun Siah, David Vigar, Lap Chan:
A study of the linearity between Ion and log Ioff of modern MOS transistors and its application to stress engineering. Microelectron. Reliab. 48(4): 497-503 (2008) - [j2]Wai Shing Lau, K. S. See, Chee Wee Eng, W. K. Aw, Kang-Hyun Jo, K. C. Tee, James Y. M. Lee, Elgin K. B. Quek, H. S. Kim, Simon T. H. Chan, Lap Chan:
Anomalous narrow width effect in p-channel metal-oxide-semiconductor surface channel transistors using shallow trench isolation technology. Microelectron. Reliab. 48(6): 919-922 (2008) - [j1]Wai Shing Lau, Peizhen Yang, V. Ho, L. F. Toh, Y. Liu, Soh Yun Siah, Lap Chan:
An explanation of the dependence of the effective saturation velocity on gate voltage in sub-0.1 µm metal-oxide-semiconductor transistors by quasi-ballistic transport theory. Microelectron. Reliab. 48(10): 1641-1648 (2008) - 2006
- [c2]Wai Shing Lau, Kin-Hong Lee, Kwong-Sak Leung:
A hybridized genetic parallel programming based logic circuit synthesizer. GECCO 2006: 839-846 - 2005
- [c1]Wai Shing Lau, Gang Li, Kin-Hong Lee, Kwong-Sak Leung, Sin Man Cheang:
Multi-logic-Unit Processor: A Combinational Logic Circuit Evaluation Engine for Genetic Parallel Programming. EuroGP 2005: 167-177
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