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ORCIDCarol Q. Tong
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2020 – today
- 2025
[j8]Qiao Tong, Xinsong Yang, Changjun Gu, Yaping Sun
, Housheng Su:
Monotone decreasing LKF method for synchronization of heterogeneous nonlinear switched time-delay multi-agent systems with an uncertain target. Commun. Nonlinear Sci. Numer. Simul. 151: 109090 (2025)- 2024
- [j7]Yushi Yang, Abdelwahab Kawafi, Qiao Tong, Erika Kague, Chrissy L. Hammond, C. Patrick Royall:
Tuning collective behaviour in zebrafish with genetic modification. PLoS Comput. Biol. 20(10): 1012034 (2024) - [c8]Ruixiong Wang, Alin Achim, Renata Raele-Rolfe, Qiao Tong, Dylan Bergen, Chrissy L. Hammond, Stephen Cross:
RoTIR: Rotation-Equivariant Network and Transformers for Zebrafish Scale Image Registration. MIUA (1) 2024: 285-299
1990 – 1999
- 1997
- [j6]Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana, Carol Q. Tong:
Operational and Test Performance in the Presence of Built-in Current Sensors. VLSI Design 5(3): 285-298 (1997) - 1995
- [c7]Ding Lu, Carol Q. Tong:
High level fault modeling of asynchronous circuits. VTS 1995: 190-195 - 1994
- [j5]Yashwant K. Malaiya, Anura P. Jayasumana, Carol Q. Tong, Sankaran M. Menon:
Resolution Enhancement in IDDQ Testing for Large ICs. VLSI Design 1(4): 277-284 (1994) - [c6]Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana, Carol Q. Tong:
The Effect of Built-In Current Sensors (BICS) on Operational and Test Performance. VLSI Design 1994: 187-190 - 1992
- [c5]Ding Lu, Carol Q. Tong:
Multiple Fault Detection in CMOS Logic Circuits. ICCD 1992: 373-376 - [c4]Qiao Tong:
Built-in current self-testing scheme (BICST) for CMOS logic circuits. VTS 1992: 304-308 - 1991
- [j4]Qiao Tong, Niraj K. Jha:
Design of C-testable DCVS binary array dividers. IEEE J. Solid State Circuits 26(2): 134-141 (1991) - [j3]Niraj K. Jha, Qiao Tong:
Robustly testable static CMOS parity trees derived from binary decision diagrams. IEEE J. Solid State Circuits 26(11): 1728-1733 (1991) - [c3]Yashwant K. Malaiya, Anura P. Jayasumana, Qiao Tong, Sankaran M. Menon:
Enhancement of resolution in supply current based testing for large ICs. VTS 1991: 291-296 - 1990
- [j2]Niraj K. Jha, Qiao Tong:
Testing of multiple-output domino logic (MODL) CMOS circuits. IEEE J. Solid State Circuits 25(3): 800-805 (1990) - [j1]Qiao Tong, Niraj K. Jha:
Testing of zipper CMOS logic circuits. IEEE J. Solid State Circuits 25(3): 877-880 (1990) - [c2]Niraj K. Jha, Qiao Tong:
Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring. EURO-DAC 1990: 350-354 - [c1]Niraj K. Jha, Carol Q. Tong:
Design of robustly testable static CMOS parity trees derived from binary decision diagrams. ICCD 1990: 103-106
Coauthor Index
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