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ORCIDToshiaki Kitamura
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2020 – today
- 2021
[c10]Hironori Kasahara, Keiji Kimura, Toshiaki Kitamura, Hiroki Mikami, Kazutaka Morita, Kazuki Fujita, Kazuki Yamamoto, Tohma Kawasumi
:
OSCAR Parallelizing and Power Reducing Compiler and API for Heterogeneous Multicores : (Invited Paper). PEHC@SC 2021: 10-19- 2020
- [c9]Yasushi Horii, Airi Tamaki, Wenjia Hong, Toshiaki Kitamura, K. Wasano:
A Transmission-Line-Based Cochlear Standing Wave Model To Elucidate Mechanism of Human Auditory System. EMBC 2020: 2328-2331
2010 – 2019
- 2019
- [c8]Wenjia Hong, Airi Tamaki, Toshiaki Kitamura, Yasushi Horii:
Possibility of Acoustic Resonance in Hair Cells in Human's Auditory System. EMBC 2019: 2891-2894 - [c7]Tomoya Kashimata, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara:
Cascaded DMA Controller for Speedup of Indirect Memory Access in Irregular Applications. IA3@SC 2019: 71-76 - 2012
- [j5]Toshiaki Kitamura:
FDTD Analysis of a Near-Field Optical Disk with a Ridged-Square Nano-Aperture. IEICE Trans. Electron. 95-C(6): 1110-1116 (2012) - 2010
- [j4]Toshiaki Kitamura, Shingo Iwata:
Analysis of a Near-Field Optical Disk with an Acute-Edged Metallic Nano-Aperture. IEICE Trans. Electron. 93-C(9): 1474-1477 (2010) - [j3]Toshiaki Kitamura, Yuya Matsunami:
Numerical Analysis of DWDD Disk with Control Layer. IEICE Trans. Electron. 93-C(12): 1713-1716 (2010)
2000 – 2009
- 2008
- [j2]Takahiro Sasaki, Yuji Ichikawa, Tetsuo Hironaka, Toshiaki Kitamura, Toshio Kondo:
Evaluation of low-energy and high-performance processor using variable stages pipeline technique. IET Comput. Digit. Tech. 2(3): 230-238 (2008) - 2007
- [j1]Taiji Sasaoka, Hideyuki Kawabata, Toshiaki Kitamura:
A MATLAB-Based Code Generator for Parallel Sparse Matrix Computations Utilizing PSBLAS. IEICE Trans. Inf. Syst. 90-D(1): 2-12 (2007) - 2004
- [c6]Hideyuki Kawabata, Mutsumi Suzuki, Toshiaki Kitamura:
A MATLAB-Based Code Generator for Sparse Matrix Computations. APLAS 2004: 280-295 - 2001
- [c5]Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori:
A high-speed dynamic instruction scheduling scheme for superscalar processors. MICRO 2001: 225-236
1990 – 1999
- 1995
- [c4]Yasuhiko Nakashima, Toshiaki Kitamura, Hideo Tamura, Masaaki Takiuchi, Ken'ichi Miura:
Scalar Processor of the VPP500 Parallel Supercomputer. International Conference on Supercomputing 1995: 348-356
1980 – 1989
- 1983
- [c3]Shinji Tomita, Kiyoshi Shibayama, Toshiaki Kitamura, Toshiyuki Nakata, Hiroshi Hagiwara:
A User-Microprogrammable, Local Host Computer With Low-Level Parallelism. ISCA 1983: 151-157 - 1980
- [c2]Kiyoshi Shibayama, Shinji Tomita, Hiroshi Hagiwara, Katsuhiro Yamazaki, Toshiaki Kitamura:
Performance Evaluation and Improvement of a Dynamically Microprogrammable Computer with Low-Level Parallelism. IFIP Congress 1980: 181-186 - [c1]Shinji Tomita, Kiyoshi Shibayama, Toshiaki Kitamura, Hiroshi Hagiwara:
Performance evaluation and improvement of a dynamically microprogrammable computer with low-level parallelism. MICRO 1980: 79-89
Coauthor Index
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