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ORCIDMustafa Celik
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2010 – 2019
- 2019
[c13]Mustafa Celik
, Oguz Kaan Hancioglu, Seta Bogosyan, Michal Bastl, Jan Najman, Robert Grepl:
Cascade Control of SATCOM on the Move (SOTM) Antennas with Jacobian Operator. ICCMA 2019: 416-422- [c12]Baris Aykent, Kadir Koca, Mustafa Celik:
System Identification-Based Dynamics Control for X-Y Pedestal Satellite Antenna. ICCMA 2019: 428-437
2000 – 2009
- 2009
- [c11]Ayhan A. Mutlu, Jiayong Le, Ruben Molina, Mustafa Celik:
A parametric approach for handling local variation effects in timing analysis. DAC 2009: 126-129 - [c10]Ayhan A. Mutlu, Jiayong Le, Ruben Molina, Mustafa Celik:
Parametric analysis to determine accurate interconnect extraction corners for design performance. ISQED 2009: 419-423 - 2008
- [j4]Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi:
Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6): 1041-1054 (2008) - 2007
- [c9]Ayhan A. Mutlu, Kelvin J. Le, Mustafa Celik, Dar-sun Tsien, Garry Shyu, Long-Ching Yeh:
An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization. ISQED 2007: 677-684 - 2005
- [c8]Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi:
Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations. ICCAD 2005: 844-851 - 2001
- [c7]Yi-Chang Lu, Kaustav Banerjee, Mustafa Celik, Robert W. Dutton:
A fast analytical technique for estimating the bounds of on-chip clock wire inductance. CICC 2001: 241-244 - [c6]Yi-Chang Lu, Mustafa Celik, Tak Young, Lawrence T. Pileggi:
Min/max On-Chip Inductance Models and Delay Metrics. DAC 2001: 341-346
1990 – 1999
- 1999
- [j3]Mustafa Celik, Lawrence T. Pileggi:
Metrics and bounds for phase delay and signal attenuation in RC(L)clock trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(3): 293-300 (1999) - [c5]Emrah Acar, Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi:
S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric. Great Lakes Symposium on VLSI 1999: 60-63 - [c4]Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi:
Practical considerations for passive reduction of RLC circuits. ICCAD 1999: 214-220 - 1998
- [j2]Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi:
PRIMA: passive reduced-order interconnect macromodeling algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8): 645-654 (1998) - 1997
- [j1]Mustafa Celik, Andreas C. Cangellaris:
Simulation of multiconductor transmission lines using Krylov subspace order-reduction techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(5): 485-496 (1997) - [c3]Zhijiang He, Mustafa Celik, Lawrence T. Pileggi:
SPIE: Sparse Partial Inductance Extraction. DAC 1997: 137-140 - [c2]Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi:
PRIMA: passive reduced-order interconnect macromodeling algorithm. ICCAD 1997: 58-65 - 1996
- [c1]Mustafa Celik, Andreas C. Cangellaris:
A general dispersive multiconductor transmission line model for interconnect simulation in SPICE. ICCAD 1996: 563-568
Coauthor Index
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