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2010 – 2019
- 2014
[c9]Tsu-Wei Tseng, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai:
A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage. VLSI-DAT 2014: 1-4- 2013
- [c8]Chang-Tzu Lin, Tsu-Wei Tseng, Yung-Fa Chou, Chia-Hsin Lee, Ding-Ming Kwai:
Enabling inter-die co-optimization in 3-D IC with TSVs. VLSI-DAT 2013: 1-4 - 2012
- [j9]Ting-Ju Chen, Jin-Fu Li, Tsu-Wei Tseng:
Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(6): 930-940 (2012) - [c7]Chang-Tzu Lin, Chia-Hsin Lee, Tsu-Wei Tseng, Ding-Ming Kwai, Yung-Fa Chou:
3-D centric technology and realization with TSV. VLSI-DAT 2012: 1-4 - 2011
- [j8]Tsu-Wei Tseng, Jin-Fu Li:
SETBIST: An Soft-Error Tolerant Built-In Self-Test Scheme for Random Access Memories. J. Inf. Sci. Eng. 27(2): 643-656 (2011) - [j7]Chih-Sheng Hou, Jin-Fu Li, Tsu-Wei Tseng:
Memory Built-in Self-Repair Planning Framework for RAMs in SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1731-1743 (2011) - [j6]Tsu-Wei Tseng, Jin-Fu Li:
A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 19(11): 1983-1995 (2011) - 2010
- [j5]Tsu-Wei Tseng, Jin-Fu Li, Chih-Sheng Hou:
A Built-in Method to Repair SoC RAMs in Parallel. IEEE Des. Test Comput. 27(6): 46-57 (2010) - [j4]Tsu-Wei Tseng, Yu-Jen Huang, Jin-Fu Li:
DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1628-1639 (2010) - [j3]Tsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu:
ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs. IEEE Trans. Very Large Scale Integr. Syst. 18(6): 921-932 (2010) - [j2]Jin-Fu Li, Tsu-Wei Tseng, Chih-Sheng Hou:
Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults. IEEE Trans. Very Large Scale Integr. Syst. 18(9): 1361-1366 (2010) - [c6]Tsu-Wei Tseng, Chih-Sheng Hou, Jin-Fu Li:
Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost. VTS 2010: 21-26
2000 – 2009
- 2008
- [c5]Tsu-Wei Tseng, Jin-Fu Li:
A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs. ITC 2008: 1-9 - 2007
- [j1]Chao-Da Huang, Jin-Fu Li, Tsu-Wei Tseng:
ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips. IEEE Trans. Very Large Scale Integr. Syst. 15(10): 1135-1143 (2007) - [c4]Tsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li, Alex Pao, Kevin Chiu, Eliot Chen:
A Built-In Self-Repair Scheme for Multiport RAMs. VTS 2007: 355-360 - [i1]Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey:
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories. CoRR abs/0710.4747 (2007) - 2006
- [c3]Tsu-Wei Tseng, Jin-Fu Li, Da-Ming Chang:
A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap. DATE 2006: 53-58 - [c2]Tsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu, Alex Pao, Kevin Chiu, Eliot Chen:
A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs. ITC 2006: 1-9 - 2005
- [c1]Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey:
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories. DATE 2005: 574-579
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