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ORCIDJeffrey B. Goeders
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- affiliation: University of British Columbia
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2020 – today
- 2024
[c26]Hayden Cook, Jeffrey Goeders:
Techniques for Exploring Fine-Grained LUT and Routing Aging on a 28nm FPGA. FPL 2024: 178-186- 2023
- [c25]Hayden Cook, Zephram Tripp, Brad L. Hutchings, Jeffrey Goeders:
Improving the Reliability of FPGA CRO PUFs. FPL 2023: 311-316 - [c24]Reilly McKendrick, Keenan Faulkner, Jeffrey Goeders:
Assuring Netlist-to-Bitstream Equivalence using Physical Netlist Generation and Structural Comparison. ICFPT 2023: 142-151 - 2022
- [j6]Eli Cahill
, Brad L. Hutchings, Jeffrey Goeders:
Approaches for FPGA Design Assurance. ACM Trans. Reconfigurable Technol. Syst. 15(3): 28:1-28:29 (2022) - [j5]Hayden Cook, Jacob Arscott, Brent George, Tanner Gaskin, Jeffrey Goeders, Brad L. Hutchings:
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits. ACM Trans. Reconfigurable Technol. Syst. 15(4): 41:1-41:33 (2022) - [c23]Hayden Cook, Jonathan Thompson, Zephram Tripp, Brad L. Hutchings, Jeffrey Goeders:
Cloning the Unclonable: Physically Cloning an FPGA Ring-Oscillator PUF. FPT 2022: 1-10 - [c22]Reilly McKendrick, Corey Simpson, Brent Nelson, Jeffrey Goeders:
Leveraging FPGA Primitives to Improve Word Reconstruction during Netlist Reverse Engineering. FPT 2022: 1-5 - 2021
- [c21]Benjamin James, Jeffrey Goeders:
Automated Software Compiler Techniques to Provide Fault Tolerance for Real-Time Operating Systems. DATE 2021: 1452-1455 - 2020
- [j4]Al-Shahna Jamal, Eli Cahill, Jeffrey Goeders, Steven J. E. Wilton:
Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays. ACM Trans. Reconfigurable Technol. Syst. 13(1): 4:1-4:26 (2020) - [c20]Tanner Gaskin, Hayden Cook, Wesley Stirk, Robert Lucas, Jeffrey Goeders, Brad L. Hutchings:
Using Novel Configuration Techniques for Accelerated FPGA Aging. FPL 2020: 169-175
2010 – 2019
- 2019
- [c19]Daniel Holanda Noronha, Ruizhe Zhao, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton:
On-chip FPGA Debug Instrumentation for Machine Learning Applications. FPGA 2019: 110-115 - [c18]Matthew B. Ashcraft, Jeffrey Goeders:
Synchronizing On-Chip Software and Hardware Traces for HLS-Accelerated Programs. FPT 2019: 54-62 - [c17]Daniel Holanda Noronha, Ruizhe Zhao, Zhiqiang Que, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton:
An Overlay for Rapid FPGA Debug of Machine Learning Applications. FPT 2019: 135-143 - [c16]Wesley Stirk, Jeffrey Goeders:
Implementation and Design Space Exploration of a Turbo Decoder in High-Level Synthesis. ReConFig 2019: 1-5 - 2018
- [c15]Jeffrey Goeders, Tanner Gaskin, Brad L. Hutchings:
Demand Driven Assembly of FPGA Configurations Using Partial Reconfiguration, Ubuntu Linux, and PYNQ. FCCM 2018: 149-156 - [c14]Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton:
Architecture Exploration for HLS-Oriented FPGA Debug Overlays. FPGA 2018: 209-218 - [c13]Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton:
An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug. FPL 2018: 403-410 - [c12]Matthew B. Ashcraft, Jeffrey Goeders:
Unified On-Chip Software and Hardware Debug for HLS-Accelerated Programs. FPT 2018: 354-357 - [c11]Adam Hastings, Sean Jensen, Jeffrey Goeders, Brad L. Hutchings:
Using Physical and Functional Comparisons to Assure 3rd-Party IP for Modern FPGAs. IVSW 2018: 80-86 - 2017
- [j3]Jeffrey Goeders, Steven J. E. Wilton:
Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 83-96 (2017) - [c10]Jeffrey Goeders:
Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage Devices. FCCM 2017: 136-143 - [c9]Pavan Kumar Bussa, Jeffrey Goeders, Steven J. E. Wilton:
Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques. FPL 2017: 1-4 - 2016
- [c8]Jeffrey Goeders, Steven J. E. Wilton:
Quantifying observability for in-system debug of high-level synthesis circuits. FPL 2016: 1-11 - [p2]Andrew Canis, Jongsok Choi, Blair Fort, Bain Syrowik, Ruolong Lian, Yu Ting Chen, Hsuan Hsiao, Jeffrey B. Goeders, Stephen Dean Brown, Jason Helge Anderson:
LegUp High-Level Synthesis. FPGAs for Software Programmers 2016: 175-190 - [p1]Jeffrey B. Goeders, Graham M. Holland, Lesley Shannon, Steven J. E. Wilton:
Systems-on-Chip on FPGAs. FPGAs for Software Programmers 2016: 261-283 - 2015
- [c7]Jeffrey B. Goeders, Steven J. E. Wilton:
Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs. FCCM 2015: 127-134 - [c6]Jeffrey Goeders, Steven J. E. Wilton:
Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs. FPT 2015: 40-47 - [i1]Jeffrey B. Goeders, Steven J. E. Wilton:
Allowing Software Developers to Debug HLS Hardware. CoRR abs/1508.06805 (2015) - 2014
- [j2]Jeffrey B. Goeders, Steven J. E. Wilton:
Power Aware Architecture Exploration for Field Programmable Gate Arrays. J. Low Power Electron. 10(3): 297-312 (2014) - [j1]Jason Luu, Jeffrey Goeders, Michael Wainberg, Andrew Somerville, Thien Yu, Konstantin Nasartschuk, Miad Nasr, Sen Wang, Tim Liu, Nooruddin Ahmed, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz:
VTR 7.0: Next Generation Architecture and CAD System for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 7(2): 6:1-6:30 (2014) - [c5]Eddie Hung, Jeffrey B. Goeders, Steven J. E. Wilton:
Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry. ARC 2014: 73-84 - [c4]Jeffrey B. Goeders, Steven J. E. Wilton:
Effective FPGA debug for high-level synthesis generated circuits. FPL 2014: 1-8 - 2012
- [c3]Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson:
The VTR project: architecture and CAD for FPGAs from verilog to routing. FPGA 2012: 77-86 - [c2]Jeffrey B. Goeders, Steven J. E. Wilton:
VersaPower: Power estimation for diverse FPGA architectures. FPT 2012: 229-234 - 2011
- [c1]Jeffrey B. Goeders, Guy G. F. Lemieux, Steven J. E. Wilton:
Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition. ReConFig 2011: 41-48
Coauthor Index
aka: Steven J. E. Wilton
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