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2010 – 2019
- 2014
[j3]Chun-Chuan Chi, Bing-Yang Lin, Cheng-Wen Wu
, Min-Jer Wang, Hung-Chih Lin, Ching-Nen Peng:
On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs. IEEE Des. Test 31(4): 16-26 (2014)- [j2]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2388-2401 (2014) - 2013
- [c9]Chun-Chuan Chi, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin:
3D-IC interconnect test, diagnosis, and repair. VTS 2013: 1-6 - 2012
- [j1]Erik Jan Marinissen, Chun-Chuan Chi, Mario Konijnenburg, Jouke Verbree:
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper. J. Electron. Test. 28(1): 73-92 (2012) - [c8]Chun-Chuan Chi, Yung-Fa Chou, Ding-Ming Kwai, Yu-Ying Hsiao, Cheng-Wen Wu, Yu-Tsao Hsing, Li-Ming Denq, Tsung-Hsiang Lin:
3D-IC BISR for stacked memories using cross-die spares. VLSI-DAT 2012: 1-4 - 2011
- [c7]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base. Asian Test Symposium 2011: 451-456 - [c6]Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang:
A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. DAC 2011: 771-776 - [c5]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
DfT Architecture for 3D-SICs with Multiple Towers. ETS 2011: 51-56 - [c4]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. ITC 2011: 1-10 - 2010
- [c3]Erik Jan Marinissen, Chun-Chuan Chi, Jouke Verbree, Mario Konijnenburg:
3D DfT architecture for pre-bond and post-bond testing. 3DIC 2010: 1-8 - [c2]Chun-Chuan Chi, Cheng-Wen Wu, Jin-Fu Li:
A low-cost and scalable test architecture for multi-core chips. ETS 2010: 30-35
2000 – 2009
- 2009
- [c1]Chun-Chuan Chi, Chih-Yen Lo, Te-Wen Ko, Cheng-Wen Wu:
Test Integration for SOC Supporting Very Low-Cost Testers. Asian Test Symposium 2009: 287-292
Coauthor Index
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