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2020 – today
- 2023
[j11]Hyeong-Ju Kang
, Byung-Do Yang:
AoCStream: All-on-Chip CNN Accelerator with Stream-Based Line-Buffer Architecture and Accelerator-Aware Pruning. Sensors 23(19): 8104 (2023)- [c10]Hyeong-Ju Kang:
AoCStream: All-on-Chip CNN Accelerator With Stream-Based Line-Buffer Architecture. FPGA 2023: 48 - 2022
- [i2]Hyeong-Ju Kang:
AoCStream: All-on-Chip CNN Accelerator With Stream-Based Line-Buffer Architecture. CoRR abs/2212.11438 (2022) - 2020
- [j10]Ki-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang:
Low-Area and Low-Power Latch-Based Thermometer-Code Shift-Register. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 2119-2123 (2020) - [j9]Hyeong-Ju Kang:
Accelerator-Aware Pruning for Convolutional Neural Networks. IEEE Trans. Circuits Syst. Video Technol. 30(7): 2093-2103 (2020)
2010 – 2019
- 2019
- [j8]Hyeong-Ju Kang:
Short floating-point representation for convolutional neural network inference. IEICE Electron. Express 16(2): 20180909 (2019) - [j7]Ki-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang:
Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches. IEEE Trans. Circuits Syst. II Express Briefs 66-II(8): 1386-1390 (2019) - [c9]Hyeong-Ju Kang:
Real-Time Object Detection on 640x480 Image With VGG16+SSD. FPT 2019: 419-422 - 2018
- [i1]Hyeong-Ju Kang:
Accelerator-Aware Pruning for Convolutional Neural Networks. CoRR abs/1804.09862 (2018) - 2013
- [j6]Hyeong-Ju Kang, Hee Suk Seo, Jin Kwak:
Area-efficient convolutional deinterleaver for mobile TV receiver. ACM Trans. Embed. Comput. Syst. 12(2): 28:1-28:12 (2013) - 2012
- [j5]Hyeong-Ju Kang, Byung-Do Yang:
Low-Power Time Deinterleaver for ISDB-T Receiver. IEEE Trans. Circuits Syst. II Express Briefs 59-II(10): 668-672 (2012) - 2011
- [j4]Hyeong-Ju Kang, Seung Jae Lee, Byung-Do Yang:
Area-Efficient Prefilter Architecture for a CDMA Receiver. IEEE Trans. Circuits Syst. II Express Briefs 58-II(4): 220-224 (2011) - [j3]Byung-Do Yang, Yong-Kyu Lee, Si-Woo Sung, Jae-Joong Min, Jae-Mun Oh, Hyeong-Ju Kang:
A Low Power Content Addressable Memory Using Low Swing Search Lines. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(12): 2849-2858 (2011)
2000 – 2009
- 2005
- [j2]Hyeong-Ju Kang, In-Cheol Park:
SAT-based unbounded symbolic model checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2): 129-140 (2005) - [c8]Hyeong-Ju Kang, Yongwoo Choi, Kimo Kim, In-Cheol Park, Jung-Wook Kim, Eul-Hwan Lee, Goo-Soo Gahang:
A scalable SIMD digital signal processor for high-quality multifunctional printer systems. Color Imaging: Processing, Hardcopy, and Applications 2005: 448-456 - 2003
- [c7]Hyeong-Ju Kang, In-Cheol Park:
SAT-based unbounded symbolic model checking. DAC 2003: 840-843 - [c6]Hyeong-Ju Kang, In-Cheol Park:
Pairing and ordering to reduce hardware complexity in cascade form filter design. ISCAS (4) 2003: 265-268 - [c5]Sung-Won Lee, Hyeong-Ju Kang, In-Cheol Park:
A 24-bit floating-point audio DSP controller supporting fast exponentiation. ISCAS (2) 2003: 748-751 - 2002
- [j1]In-Cheol Park, Hyeong-Ju Kang:
Digital filter synthesis based on an algorithm to generate all minimal signed digit representations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12): 1525-1529 (2002) - [c4]Hyeong-Ju Kang, In-Cheol Park:
A high-speed and low-latency Reed-Solomon decoder based on a dual-line structure. ICASSP 2002: 3180-3183 - 2001
- [c3]In-Cheol Park, Hyeong-Ju Kang:
Digital Filter Synthesis Based on Minimal Signed Digit Representation. DAC 2001: 468-473 - [c2]Hyeong-Ju Kang, In-Cheol Park:
Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders. ISCAS (2) 2001: 693-696 - 2000
- [c1]Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park:
FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders. ICCAD 2000: 51-54
Coauthor Index
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