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ORCIDFPGA 2023: Monterey, CA, USA
- Paolo Ienne, Zhiru Zhang:
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023. ACM 2023, ISBN 978-1-4503-9417-8
Keynote I
- Saman P. Amarasinghe
:
Compiler Support for Structured Data. 1-2
Session: High-Level Abstraction and Tools
- Linus Y. Wong, Jialiang Zhang, Jing Jane Li:
DONGLE: Direct FPGA-Orchestrated NVMe Storage for HLS. 3-13 - Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang:
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. 15-25 - Jiahui Xu, Emmet Murphy, Jordi Cortadella, Lana Josipovic:
Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking. 27-37 - Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri, Lana Josipovic, Paolo Ienne:
Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits. 39-45
Poster Session I
- Rakin Muhammad Shadab, Yu Zou, Sanjay Gandham, Mingjie Lin:
OMT: A Demand-Adaptive, Hardware-Targeted Bonsai Merkle Tree Framework for Embedded Heterogeneous Memory Platform. 47 - Kaveh Aasaraai, Emanuele Cesena, Rahul Maganti, Nicolas Stalder, Javier Varela, Kevin Bowers:
Cyclone-NTT: An NTT/FFT Architecture Using Quasi-Streaming of Large Datasets on DDR- and HBM-based FPGA Platforms. 47 - Hyeong-Ju Kang:
AoCStream: All-on-Chip CNN Accelerator With Stream-Based Line-Buffer Architecture. 48 - Tim Oberschulte, Jakob Marten, Holger Blume:
Fault Detection on Multi COTS FPGA Systems for Physics Experiments on the International Space Station. 48 - Meghna Mandava, Deming Chen:
Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization. 49 - Ruiqi Chen, Haoyang Zhang, Yuhanxiao Ma, Enhao Tang, Shun Li, Yanxiang Zhu, Jun Yu, Kun Wang:
Graph-OPU: An FPGA-Based Overlay Processor for Graph Neural Networks. 49 - Michael Lo, Young-kyu Choi, Weikang Qiao, Mau-Chung Frank Chang, Jason Cong:
HMLib: Efficient Data Transfer for HLS Using Host Memory. 50 - Ross Martin:
An Efficient High-Speed FFT Implementation. 50 - Tuo Dai, Bizhao Shi, Guojie Luo:
Weave: Abstraction for Accelerator Integration of Generated Modules. 51 - Zhenyu Xu, Miaoxiang Yu, Qing Yang, Yeonho Jeong, Tao Wei:
A Novel FPGA Simulator Accelerating Reinforcement Learning-Based Design of Power Converters. 51 - Lin Shu, Long Xiao, Yafang Song, Qiuxiang Fan, Guitian Fang, Jie Hao:
A Fractal Astronomical Correlator Based on FPGA Cluster with Scalability. 52 - Saya Inagaki, Mingyu Yang, Yang Li, Kazuo Sakiyama, Yuko Hara-Azumi:
Power Side-channel Countermeasures for ARX Ciphers using High-level Synthesis. 52 - Chuliang Guo, Binglei Lou, Xueyuan Liu, David Boland, Philip H. W. Leong:
Single-Batch CNN Training using Block Minifloats on FPGAs. 53
Session: Applications and Design Studies I
- Mehdi Moghaddamfar, Norman May, Christian Färber, Wolfgang Lehner, Akash Kumar:
A Study of Early Aggregation in Database Query Processing on FPGAs. 55-65 - Chaoqiang Liu, Haifeng Liu, Long Zheng, Yu Huang, Xiangyu Ye, Xiaofei Liao, Hai Jin:
FNNG: A High-Performance FPGA-based Accelerator for K-Nearest Neighbor Graph Construction. 67-77 - Wole Jaiyeoba, Nima Elyasi, Changho Choi, Kevin Skadron:
ACTS: A Near-Memory FPGA Graph Processing Framework. 79-89 - Nick Brown:
Exploring the Versal AI Engines for Accelerating Stencil-based Atmospheric Advection Simulation. 91-97
Session: Architecture, CAD, and Circuit Design
- Stefan Nikolic, Paolo Ienne:
Regularity Matters: Designing Practical FPGA Switch-Blocks. 99-109 - Colin Drewes, Olivia Weng, Keegan Ryan, Bill Hunter, Christopher McCarty, Ryan Kastner, Dustin Richmond:
Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Time-to-Digital Converters. 111-122 - Andrew Elbert Wilson, Nathan Baker, Ethan Campbell, Jackson Sahleen, Michael J. Wirthlin:
Post-Radiation Fault Analysis of a High Reliability FPGA Linux SoC. 123-133 - Longfei Fan, Chang Wu:
FPGA Technology Mapping with Adaptive Gate Decomposition. 135-140 - Jonathan W. Greene:
FPGA Mux Usage and Routability Estimates without Explicit Routing. 141-147
Banquet and Panel
- Dana How, Tim Ansell, Vaughn Betz, Chris Lavin, Ted Speers, Pierre-Emmanuel Gaillardon:
Open-source and FPGAs: Hardware, Software, Both or None? 149
Keynote II
- Jaideep Dastidar:
FPGAs and Their Evolving Role in Domain Specific Architectures: A Case Study of the AMD 400G Adaptive SmartNIC/DPU SoC. 151
Session: Deep Learning
- Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Yubo Du, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex K. Jones, Jingtong Hu, Deming Chen, Jason Cong, Peipei Zhou:
CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture. 153-164 - Alireza Khataei, Gaurav Singh, Kia Bazargan:
Approximate Hybrid Binary-Unary Computing with Applications in BERT Language Model and Image Processing. 165-175 - Lei Cai, Jing Wang, Lianfeng Yu, Bonan Yan, Yaoyu Tao, Yuchao Yang:
Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize Search. 177-183
Session: FPGA-Based Computing Engines
- Xuan Wang, Lei Gong, Jing Cao, Wenqi Lou, Weiya Wang, Chao Wang, Xuehai Zhou:
hAP: A Spatial-von Neumann Heterogeneous Automata Processor with Optimized Resource and IO Overhead on FPGA. 185-196 - Sergey Gribok, Bogdan Pasca, Martin Langhammer:
CSAIL2019 Crypto-Puzzle Solver Architecture. 197-207 - Kan Shi, Shuoxiang Xu, Yuhan Diao, David Boland, Yungang Bao:
ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration. 209-219 - Vishak Narayanan, Rohit Sahu, Jidong Sun, Henry Duwe:
BOBBER A Prototyping Platform for Batteryless Intermittent Accelerators. 221-228
Poster Session II
- Olivia Weng, Gabriel Marcano, Vladimir Loncar, Alireza Khodamoradi, Nojan Sheybani, Farinaz Koushanfar, Kristof Denolf, Javier Mauricio Duarte, Ryan Kastner:
Adapting Skip Connections for Resource-Efficient FPGA Inference. 229 - Mingqiang Huang, Yucen Liu, Sixiao Huang, Kai Li, Qiuping Wu, Hao Yu:
Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme. 229 - Bharat Sukhwani, Mohit Kapur, Alda Ohmacht, Liran Schour, Martin Ohmacht, Chris Ward, Chuck Haymes, Sameh W. Asaad:
Janus: An Experimental Reconfigurable SmartNIC with P4 Programmability and SDN Isolation. 230 - Dimitrios Gourounas, Bagus Hanindhito, Arash Fathi, Dimitar Trenev, Lizy Kurian John, Andreas Gerstlauer:
LAWS: Large-Scale Accelerated Wave Simulations on FPGAs. 230 - Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic:
Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing. 231 - Andrew David Gunter, Steven J. E. Wilton:
Towards a Machine Learning Approach to Predicting the Difficulty of FPGA Routing Problems. 231 - Zachary Susskind, Aman Arora, Alan T. L. Bacellar, Diego Leonel Cadette Dutra, Igor D. S. Miranda, Maurício Breternitz, Priscila M. V. Lima, Felipe M. G. França, Lizy K. John:
An FPGA-Based Weightless Neural Network for Edge Network Intrusion Detection. 232 - Yongzheng Chen, Gang Wu:
A Flexible Toolflow for Mapping CNN Models to High Performance FPGA-based Accelerators. 232 - Emanuele Del Sozzo, Davide Conficconi, Marco D. Santambrogio, Kentaro Sano:
Senju: A Framework for the Design of Highly Parallel FPGA-based Iterative Stencil Loop Accelerators. 233 - Jinfeng Li, Yahong Rosa Zheng:
FPGA Acceleration for Successive Interference Cancellation in Severe Multipath Acoustic Communication Channels. 233 - Sergiu Mosanu, Joshua Fixelle, Kevin Skadron, Mircea Stan:
FreezeTime: Towards System Emulation through Architectural Virtualization. 234
Session: Applications and Design Studies II
- Yuan Meng, Rajgopal Kannan, Viktor K. Prasanna:
A Framework for Monte-Carlo Tree Search on CPU-FPGA Heterogeneous Platform via on-chip Dynamic Tree Management. 235-245 - Linghao Song, Licheng Guo, Suhail Basalama, Yuze Chi, Robert F. Lucas, Jason Cong:
Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver. 247-258 - Sasindu Wijeratne, Ta-Yang Wang, Rajgopal Kannan, Viktor K. Prasanna:
Accelerating Sparse MTTKRP for Tensor Decomposition on FPGA. 259-269
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