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ORCIDAshutosh Chakraborty
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2010 – 2019
- 2013
[j6]Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Giovanni De Micheli:
Cell transformations and physical design techniques for 3D monolithic integrated circuits. ACM J. Emerg. Technol. Comput. Syst. 9(3): 19:1-19:28 (2013)- [j5]Ashutosh Chakraborty, David Z. Pan:
Skew Management of NBTI Impacted Gated Clock Trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6): 918-927 (2013) - 2012
- [c18]Yilin Zhang, Ashutosh Chakraborty, Salim Chowdhury, David Z. Pan:
Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree construction. ICCAD 2012: 137-143 - 2011
- [c17]Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Thomas Ernst
, Olivier Faynot, David Z. Pan, Giovanni De Micheli:
CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits. ASP-DAC 2011: 336-343 - [c16]Ashutosh Chakraborty, David Z. Pan:
Controlling NBTI degradation during static burn-in testing. ASP-DAC 2011: 597-602 - 2010
- [j4]Ashutosh Chakraborty, Sean X. Shi, David Z. Pan:
Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1533-1545 (2010) - [j3]Ashutosh Chakraborty, Karthik Duraisami, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino:
Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(10): 2741-2752 (2010) - [c15]Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Vasilis F. Pavlidis, Giovanni De Micheli:
Performance analysis of 3-D monolithic integrated circuits. 3DIC 2010: 1-4 - [c14]Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim:
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. ICCAD 2010: 669-674 - [c13]Ashutosh Chakraborty, David Z. Pan:
PASAP: power aware structured ASIC placement. ISLPED 2010: 395-400 - [c12]Ashutosh Chakraborty, David Z. Pan:
Skew management of NBTI impacted gated clock trees. ISPD 2010: 127-133
2000 – 2009
- 2009
- [c11]Ashutosh Chakraborty, Anurag Kumar, David Z. Pan:
RegPlace: a high quality open-source placement framework for structured ASICs. DAC 2009: 442-447 - [c10]Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan:
Analysis and optimization of NBTI induced clock skew in gated clock trees. DATE 2009: 296-299 - [c9]Ashutosh Chakraborty, David Z. Pan:
On stress aware active area sizing, gate sizing, and repeater insertion. ISPD 2009: 35-42 - 2008
- [j2]Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino:
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations. Integr. 41(1): 2-8 (2008) - [j1]Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 639-649 (2008) - [c8]Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan:
An integrated nonlinear placement framework with congestion and porosity aware buffer planning. DAC 2008: 702-707 - [c7]Ashutosh Chakraborty, Sean X. Shi, David Z. Pan:
Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices. DATE 2008: 849-855 - 2006
- [c6]Ashutosh Chakraborty, Prassanna Sithambaram, Karthik Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino:
Thermal resilient bounded-skew clock tree optimization methodology. DATE 2006: 832-837 - [c5]Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino:
Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits. ISCAS 2006 - [c4]Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Dynamic thermal clock skew compensation using tunable delay buffers. ISLPED 2006: 162-167 - [c3]Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino:
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. PATMOS 2006: 214-224 - 2005
- [c2]Ashutosh Chakraborty, Enrico Macii, Massimo Poncino:
Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding. PATMOS 2005: 297-307 - 2003
- [c1]Pradeep Varma, Ashutosh Chakraborty:
Low-Voltage, Double-Edge-Triggered Flip Flop. PATMOS 2003: 11-20
Coauthor Index
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