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ORCIDTakayuki Kamei
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2010 – 2019
- 2012
[c5]Takayuki Kamei, Keiko Ono, Masahito Kumano, Masahiro Kimura:
Predicting missing links in social networks with hierarchical dirichlet processes. IJCNN 2012: 1-8
2000 – 2009
- 2003
- [j4]Shunichi Ishiwata, Tomoo Yamakage, Yoshiro Tsuboi, Takayoshi Shimazawa, Tomoko Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, Tomoya Kodama, Nobu Matsumoto, Takayuki Kamei, Mitsuo Saito, Takashi Miyamori, Goichi Ootomo, Masataka Matsui:
A single-chip MPEG-2 codec based on customizable media embedded processor. IEEE J. Solid State Circuits 38(3): 530-540 (2003) - 2002
- [c4]Shunichi Ishiwata, Tomoo Yamakage, Yoshiro Tsuboi, Takayoshi Shimazawa, Tomoko Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, Tomoya Kodama, Nobu Matsumoto, Takayuki Kamei, Takashi Miyamori, Goichi Ootomo, Masataka Matsui:
A single-chip MPEG-2 codec based on customizable media microprocessor. CICC 2002: 163-166 - 2000
- [j3]Nobuhiro Ide, Masashi Hirano, Yukio Endo, Shin-ichi Yoshioka, Hiroaki Murakami, Atsushi Kunimatsu, Toshinori Sato
, Takayuki Kamei, Toyoshi Okada, Masakazu Suzuoki:
2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing. IEEE J. Solid State Circuits 35(7): 1025-1033 (2000) - [j2]Atsushi Kunimatsu, Nobuhiro Ide, Toshinori Sato, Yukio Endo, Hiroaki Murakami, Takayuki Kamei, Masashi Hirano, Fujio Ishihara, Haruyuki Tago, Masaaki Oka, Akio Ohba, Teiji Yutaka, Toyoshi Okada, Masakazu Suzuoki:
Vector Unit Architecture for Emotion Synthesis. IEEE Micro 20(2): 40-47 (2000) - [c3]Takayuki Kamei, Hideaki Takeda, Yukio Ootaguro, Takayoshi Shimazawa, Kazuhiko Tachibana, Shin'ichi Kawakami, Seiji Norimatsu, Fujio Ishihara, Toshinori Sato, Hiroaki Murakami, Nobuhiro Ide, Yukio Endo, Akira Aono, Atsushi Kunimatsu:
300MHz design methodology of VU for emotion synthesis. ASP-DAC 2000: 635-640
1990 – 1999
- 1999
- [j1]Junji Yamamoto, Takashi Fujiwara, T. Komeda, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano:
Performance evaluation of SNAIL: A multiprocessor based on the simple serial synchronized multistage interconnection network architecture. Parallel Comput. 25(9): 1081-1103 (1999) - 1998
- [c2]Takashi Midorikawa, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano:
The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip. ASP-DAC 1998: 337-338 - 1997
- [c1]Takayuki Kamei, Masashi Sasahara, Hideharu Amano:
An LSI implementation of the simple serial synchronized multistage interconnection network. ASP-DAC 1997: 673-674
Coauthor Index
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