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Pierre Michaud
Person information
- affiliation: IRISA/INRIA, Rennes, France
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2020 – today
- 2022
- [j15]Pierre Michaud
, Anis Peysieux
:
HAIR: Halving the Area of the Integer Register File with Odd/Even Banking. ACM Trans. Archit. Code Optim. 19(4): 51:1-51:25 (2022) - 2020
- [j14]Pierre Michaud
:
Exploiting Thermal Transients With Deterministic Turbo Clock Frequency. IEEE Comput. Archit. Lett. 19(1): 43-46 (2020)
2010 – 2019
- 2018
- [j13]Pierre Michaud
:
An Alternative TAGE-like Conditional Branch Predictor. ACM Trans. Archit. Code Optim. 15(3): 30:1-30:23 (2018) - 2016
- [j12]Mun-Kyu Lee, Pierre Michaud
, Jeong Seop Sim, DaeHun Nyang:
A simple proof of optimality for the MIN cache replacement policy. Inf. Process. Lett. 116(2): 168-170 (2016) - [j11]Pierre Michaud
:
Some Mathematical Facts About Optimal Cache Replacement. ACM Trans. Archit. Code Optim. 13(4): 50:1-50:19 (2016) - [c16]Pierre Michaud
:
Best-offset hardware prefetching. HPCA 2016: 469-480 - 2015
- [j10]Ricardo A. Velásquez
, Pierre Michaud
, André Seznec:
BADCO: Behavioral Application-Dependent Superscalar Core Models. Int. J. Parallel Program. 43(1): 130-157 (2015) - [j9]Pierre Michaud
, Andrea Mondelli, André Seznec:
Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters. ACM Trans. Archit. Code Optim. 12(3): 28:1-28:22 (2015) - [c15]Arthur Perais
, André Seznec, Pierre Michaud
, Andreas Sembrant, Erik Hagersten:
Cost-effective speculative scheduling in high performance processors. ISCA 2015: 247-259 - [c14]Stijn Eyerman, Pierre Michaud
, Wouter Rogiest:
Revisiting symbiotic job scheduling. ISPASS 2015: 124-134 - [c13]Andreas Sembrant, Trevor E. Carlson
, Erik Hagersten, David Black-Schaffer, Arthur Perais
, André Seznec, Pierre Michaud:
Long term parking (LTP): criticality-aware resource allocation in OOO processors. MICRO 2015: 334-346 - 2014
- [j8]Stijn Eyerman, Pierre Michaud
, Wouter Rogiest:
Multiprogram Throughput Metrics: A Systematic Approach. ACM Trans. Archit. Code Optim. 11(3): 34:1-34:26 (2014) - 2013
- [j7]Pierre Michaud
:
Demystifying multicore throughput metrics. IEEE Comput. Archit. Lett. 12(2): 63-66 (2013) - [c12]Ricardo A. Velásquez
, Pierre Michaud
, André Seznec:
Selecting benchmark combinations for the evaluation of multicore throughput. ISPASS 2013: 173-182 - 2012
- [c11]Ricardo A. Velásquez, Pierre Michaud, André Seznec:
BADCO: Behavioral Application-Dependent Superscalar Core model. ICSAMOS 2012: 58-67 - 2011
- [c10]Pierre Michaud
:
Replacement policies for shared caches on symmetric multicores: a programmer-centric point of view. HiPEAC 2011: 187-196 - 2010
- [c9]Pierre Michaud
, Yiannakis Sazeides, André Seznec
:
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses. Conf. Computing Frontiers 2010: 237-246
2000 – 2009
- 2009
- [c8]Pierre Michaud:
Online compression of cache-filtered address traces. ISPASS 2009: 185-194 - 2007
- [j6]Pierre Michaud
, André Seznec, Damien Fetis, Yiannakis Sazeides, Theofanis Constantinou:
A study of thread migration in temperature-constrained multicores. ACM Trans. Archit. Code Optim. 4(2): 9 (2007) - 2006
- [j5]André Seznec, Pierre Michaud:
A case for (partially) TAgged GEometric history length branch prediction. J. Instr. Level Parallelism 8 (2006) - 2005
- [j4]Pierre Michaud:
A PPM-like, Tag-based Predictor. J. Instr. Level Parallelism 7 (2005) - [j3]Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud
, Damien Fetis, André Seznec:
Performance implications of single thread migration on a chip multi-core. SIGARCH Comput. Archit. News 33(4): 80-91 (2005) - 2004
- [c7]Pierre Michaud
:
Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration. HPCA 2004: 186-197 - 2003
- [c6]Pierre Michaud
:
A statistical model of skewed-associativity. ISPASS 2003: 204-213 - 2002
- [c5]Pierre Michaud, Christian Saguez:
A Learning Grid for the multichallenge school ECP. LeGE-WG 1 2002 - 2001
- [j2]Pierre Michaud, André Seznec, Stéphan Jourdan:
An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors. Int. J. Parallel Program. 29(1): 35-58 (2001) - [c4]Pierre Michaud
, André Seznec:
Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors. HPCA 2001: 27-36
1990 – 1999
- 1999
- [c3]Pierre Michaud
, André Seznec, Stéphan Jourdan:
Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors. IEEE PACT 1999: 2-10 - 1997
- [j1]Pierre Michaud:
Clustering techniques. Future Gener. Comput. Syst. 13(2-3): 135-147 (1997) - [c2]Pierre Michaud
, André Seznec, Richard Uhlig:
Trading Conflict and Capacity Aliasing in Conditional Branch Predictors. ISCA 1997: 292-303 - 1996
- [c1]André Seznec, Stéphan Jourdan, Pascal Sainrat, Pierre Michaud
:
Multiple-Block Ahead Branch Predictors. ASPLOS 1996: 116-127
Coauthor Index
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last updated on 2024-04-25 05:55 CEST by the dblp team
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