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2020 – today
- 2024
[c19]Xiaowu Sun, Theofilos Belmpas, Ortal Yona Senouf, Emmanuel Abbe, Pascal Frossard, Bernard De Bruyne, Olivier Muller, Stéphane Fournier, Thabo Mahendiran, Dorina Thanou:
Graph Neural Network based Future Clinical Events Prediction from Invasive Coronary Angiography. ISBI 2024: 1-5- 2023
- [j8]Bruno Ferres
, Olivier Muller, Frédéric Rousseau:
A Chisel Framework for Flexible Design Space Exploration through a Functional Approach. ACM Trans. Design Autom. Electr. Syst. 28(4): 63:1-63:31 (2023) - [c18]Riccardo Tenderini, Federico Betti, Ortal Yona Senouf, Olivier Muller, Simone Deparis, Annalisa Buffa, Emmanuel Abbe:
Can Knowledge Transfer Techniques Compensate for the Limited Myocardial Infarction Data by Leveraging Hæmodynamics? An in silico Study. AIME 2023: 218-228 - [i2]Bruno Ferres, Olivier Muller, Frédéric Rousseau:
A Chisel Framework for Flexible Design Space Exploration through a Functional Approach. CoRR abs/2302.12702 (2023) - 2022
- [j7]Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groléat, Frédéric Pétrot:
Toward Agile Hardware Designs With Chisel: A Network Use Case. IEEE Des. Test 39(1): 77-84 (2022) - 2021
- [j6]Arif Sasongko, I. M. Narendra Kumara, Arief Wicaksana, Frédéric Rousseau, Olivier Muller:
Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple Streams. ACM Trans. Reconfigurable Technol. Syst. 14(3): 14:1-14:25 (2021) - [c17]Bruno Ferres, Olivier Muller, Frédéric Rousseau:
Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration. RSP 2021: 64-70 - 2020
- [c16]Bruno Ferres, Olivier Muller, Frédéric Rousseau:
Chisel Usecase: Designing General Matrix Multiply for FPGA. ARC 2020: 61-72 - [c15]Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groléat, Frédéric Pétrot:
(System)Verilog to Chisel Translation for Faster Hardware Design. RSP 2020: 1-7
2010 – 2019
- 2019
- [j5]Olivier Muller, Adrien Prost-Boucle, Alban Bourge, Frédéric Pétrot:
Efficient Decompression of Binary Encoded Balanced Ternary Sequences. IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1962-1966 (2019) - 2018
- [c14]Georgios Christodoulis, François Broquedis, Olivier Muller, Manuel Selva, Frederic Desprez:
An FPGA target for the StarPU heterogeneous runtime system. ReCoSoC 2018: 1-8 - [c13]Thomas Baumela, Olivier Gruber, Olivier Muller, Frédéric Pétrot:
Message-Oriented Devices on FPGAs. RSP 2018: 8-14 - 2017
- [c12]Arief Wicaksana, Alban Bourge, Olivier Muller, Arif Sasongko, Frédéric Rousseau:
Prototyping dynamic task migration on heterogeneous reconfigurable systems. RSP 2017: 16-22 - 2016
- [j4]Alban Bourge, Olivier Muller, Frédéric Rousseau:
Generating Efficient Context-Switch Capable Circuits through Autonomous Design Flow. ACM Trans. Reconfigurable Technol. Syst. 10(1): 9:1-9:23 (2016) - [c11]Simon Pontie, Alban Bourge, Adrien Prost-Boucle, Paolo Maistri, Olivier Muller, Régis Leveugle, Frédéric Rousseau:
HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic. DSD 2016: 511-518 - [c10]Arief Wicaksana, Alban Bourge, Olivier Muller, Frédéric Rousseau:
Demonstration of a context-switch method for heterogeneous reconfigurable systems. FPL 2016: 1 - [c9]Arief Wicaksana, Adrien Prost-Boucle, Olivier Muller, Frédéric Rousseau, Arif Sasongko:
On-board non-regression test of HLS tools targeting FPGA. RSP 2016: 41-47 - [i1]Arief Wicaksana, Alban Bourge, Olivier Muller, Frédéric Rousseau:
Demonstration of a context-switch method for heterogeneous reconfigurable systems. CoRR abs/1611.06796 (2016) - 2015
- [c8]Alban Bourge, Olivier Muller, Frédéric Rousseau:
Automatic High-Level Hardware Checkpoint Selection for Reconfigurable Systems. FCCM 2015: 155-158 - [c7]Alban Bourge, Olivier Muller, Frédéric Rousseau:
A Novel Method for Enabling FPGA Context-Switch (Abstract Only). FPGA 2015: 261 - 2014
- [j3]Adrien Prost-Boucle, Olivier Muller, Frédéric Rousseau:
Fast and standalone Design Space Exploration for High-Level Synthesis under resource constraints. J. Syst. Archit. 60(1): 79-93 (2014) - 2013
- [c6]Adrien Prost-Boucle, Olivier Muller, Frédéric Rousseau:
A Fast and Autonomous HLS Methodology for Hardware Accelerator Generation under Resource Constraints. DSD 2013: 201-208 - 2012
- [c5]Yan Xu, Olivier Muller, Pierre-Henri Horrein, Frédéric Pétrot:
HCM: An abstraction layer for seamless programming of DPR FPGA. FPL 2012: 583-586 - 2010
- [j2]Olivier Muller, Amer Baghdadi, Michel Jézéquel:
Parallelism Efficiency in Convolutional Turbo Decoding. EURASIP J. Adv. Signal Process. 2010 (2010)
2000 – 2009
- 2009
- [j1]Olivier Muller, Amer Baghdadi, Michel Jézéquel:
From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 92-102 (2009) - 2008
- [c4]Olivier Muller, Amer Baghdadi, Michel Jézéquel:
From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding. IEEE International Workshop on Rapid System Prototyping 2008: 128-134 - 2007
- [c3]Hazem Moussa, Olivier Muller, Amer Baghdadi, Michel Jézéquel:
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding. DATE 2007: 654-659 - 2006
- [c2]Olivier Muller, Amer Baghdadi, Michel Jézéquel:
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding. DATE 2006: 1330-1335 - [c1]Olivier Muller, Amer Baghdadi, Michel Jézéquel:
On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference. GLOBECOM 2006
Coauthor Index
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last updated on 2024-09-09 00:15 CEST by the dblp team
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