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"(System)Verilog to Chisel Translation for Faster Hardware Design."

Jean Bruant et al. (2020)

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DOI: 10.1109/RSP51120.2020.9244852

access: closed

type: Conference or Workshop Paper

metadata version: 2020-11-10

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  dblp key:
  - conf/rsp/BruantHMGP20
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  - https://dblp.org/rec/conf/rsp/BruantHMGP20
Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groléat, Frédéric Pétrot:
(System)Verilog to Chisel Translation for Faster Hardware Design. RSP 2020: 1-7

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