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ORCIDJorge Juan
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2010 – 2019
- 2017
[j5]Paulino Ruiz-de-Clavijo, Enrique Ostúa
, Manuel Jesús Bellido Díaz, Jorge Juan, Julian Viejo, David Guerrero Martos:
Minimalistic SDHC-SPI hardware reader module for boot loader applications. Microelectron. J. 67: 32-37 (2017)- 2012
- [j4]Julian Viejo, Jose Ignacio Villar, Jorge Juan, Alejandro Millán, Enrique Ostúa, Juan Quiros:
Long-term on-chip verification of systems with logical events scattered in time. Microprocess. Microsystems 36(5): 402-408 (2012) - [c6]Jorge Juan, Julian Viejo, Manuel J. Bellido:
Network Time Synchronization: A Full Hardware Approach. PATMOS 2012: 225-234 - 2011
- [j3]David Guerrero Martos, Alejandro Millán, Jorge Juan, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo:
Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells. J. Low Power Electron. 7(3): 444-452 (2011) - [j2]Julian Viejo, Jorge Juan, Manuel Jesús Bellido Díaz, Alejandro Millán, Paulino Ruiz-de-Clavijo:
Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation. IEEE Trans. Instrum. Meas. 60(12): 3961-3963 (2011) - 2010
- [j1]Alejandro Millán, Manuel J. Bellido, Jorge Juan, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo:
Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies. J. Low Power Electron. 6(1): 93-102 (2010) - [c5]Julian Viejo, Jose Ignacio Villar, Jorge Juan, Alejandro Millán, Manuel Jesús Bellido Díaz, Enrique Ostúa:
Design and implementation of a suitable core for on-chip long-term verification. SIES 2010: 234-237
2000 – 2009
- 2009
- [c4]Jose Ignacio Villar, Jorge Juan, Manuel J. Bellido:
Efficient techniques and methodologies for embedded system design usign free hardware and open standards. FPL 2009: 719-720 - 2008
- [c3]Alejandro Millán, Jorge Juan, Manuel J. Bellido, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo:
Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. PATMOS 2008: 389-398 - 2007
- [c2]Julian Viejo, Alejandro Millán, Manuel J. Bellido, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Alejandro Muñoz:
Design of a FFT/IFFT module as an IP core suitable for embedded systems. SIES 2007: 337-340 - 2006
- [c1]Julian Viejo, Manuel J. Bellido, Alejandro Millán, Enrique Ostúa, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos:
Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements. IES 2006: 1-7
Coauthor Index
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