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Journal Articles
- 2022
[j20]Kai Lu, Yaohua Wang
, Yang Guo, Chun Huang, Sheng Liu, Ruibo Wang, Jianbin Fang, Tao Tang, Zhaoyun Chen, Biwei Liu, Zhong Liu, Yuanwu Lei, Haiyan Sun:
MT-3000: a heterogeneous multi-zone processor for HPC. CCF Trans. High Perform. Comput. 4(2): 150-164 (2022)- 2021
- [j19]Yaohua Wang, Chen Li, Chang Liu, Sheng Liu, Yuanwu Lei, Jian Zhang, Yang Zhang, Yang Guo:
Advancing DSP into HPC, AI, and beyond: challenges, mechanisms, and future directions. CCF Trans. High Perform. Comput. 3(1): 114-125 (2021) - 2019
- [j18]Sheng Ma, Yuanwu Lei, Libo Huang, Zhiying Wang:
MT-DMA: A DMA Controller Supporting Efficient Matrix Transposition for Digital Signal Processing. IEEE Access 7: 5808-5818 (2019) - [j17]Pengfei Wang, Yuanwu Lei, Yong Dou:
Pair-HMM accelerator based on non-cooperative structure. IEICE Electron. Express 16(15): 20190402 (2019) - 2018
- [j16]Xiaowen Chen, Yuanwu Lei, Zhonghai Lu, Shuming Chen:
A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1953-1966 (2018) - 2017
- [j15]Baozhou Zhu, Yuanwu Lei, Yuanxi Peng, Tingting He:
Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(4): 892-905 (2017) - 2016
- [j14]Yueqing Wang, Yong Dou, Xinwang Liu, Yuanwu Lei:
PR-ELM: Parallel regularized extreme learning machine based on cluster. Neurocomputing 173: 1073-1081 (2016) - [j13]Yueqing Wang, Zhige Xie, Kai Xu, Yong Dou, Yuanwu Lei:
An efficient and effective convolutional auto-encoder extreme learning machine network for 3d feature learning. Neurocomputing 174: 988-998 (2016) - [j12]Qi Lv, Xin Niu, Yong Dou, Jiaqing Xu, Yuanwu Lei:
Classification of Hyperspectral Remote Sensing Image Using Hierarchical Local-Receptive-Field-Based Extreme Learning Machine. IEEE Geosci. Remote. Sens. Lett. 13(3): 434-438 (2016) - 2015
- [j11]Song Guo, Yong Dou, Yuanwu Lei, Guiming Wu:
A deeply-pipelined FPGA-based SpMV accelerator with a hardware-friendly storage scheme. IEICE Electron. Express 12(11): 20150161 (2015) - [j10]Song Guo, Yong Dou, Yuanwu Lei, Rongchun Li, Yu Li:
An efficient multi-standard QC-LDPC decoder based on the row-layered decoding algorithm. IEICE Electron. Express 12(13): 20150356 (2015) - 2014
- [j9]Yueqing Wang, Yong Dou, Song Guo, Yuanwu Lei, Dan Zou:
CPU-GPU hybrid parallel strategy for cosmological simulations. Concurr. Comput. Pract. Exp. 26(3): 748-765 (2014) - [j8]Lei Guo, Yuhua Tang, Yuanwu Lei, Yong Dou, Jie Zhou:
Transpose-free variable-size FFT accelerator based on-chip SRAM. IEICE Electron. Express 11(15): 20140171 (2014) - [j7]Yuanwu Lei, Lei Guo, Yong Dou, Sheng Ma, Jinbo Xu:
FPGA Implementation of a Special-Purpose VLIW Structure for Double-Precision Elementary Function. ACM Trans. Reconfigurable Technol. Syst. 7(2): 8:1-8:21 (2014) - 2013
- [j6]Lei Guo, Yuhua Tang, Yong Dou, Yuanwu Lei, Meng Ma, Jie Zhou:
Window Memory Layout Scheme for Alternate Row-Wise/Column-Wise Matrix Access. IEICE Trans. Inf. Syst. 96-D(12): 2765-2775 (2013) - [j5]Yuanwu Lei, Yong Dou, Lei Guo, Jinbo Xu, Jie Zhou, Yazhuo Dong, Hongjian Li:
VLIW coprocessor for IEEE-754 quadruple-precision elementary functions. ACM Trans. Archit. Code Optim. 10(3): 12:1-12:22 (2013) - [j4]Yuanwu Lei, Yong Dou, Yazhuo Dong, Jie Zhou, Fei Xia:
FPGA implementation of an exact dot product and its application in variable-precision floating-point arithmetic. J. Supercomput. 64(2): 580-605 (2013) - 2012
- [j3]Rongchun Li, Yong Dou, Yuanwu Lei, Shi-Ce Ni, Song Guo:
Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA. IEICE Trans. Commun. 95-B(5): 1602-1611 (2012) - 2011
- [j2]Yuanwu Lei, Yong Dou, Jie Zhou:
FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic. IEICE Trans. Inf. Syst. 94-D(11): 2173-2183 (2011) - 2010
- [j1]Yong Dou, Jie Zhou, Guiming Wu, Jingfei Jiang, Yuanwu Lei, Shi-Ce Ni:
A Unified Co-Processor Architecture for Matrix Decomposition. J. Comput. Sci. Technol. 25(4): 874-885 (2010)
Conference and Workshop Papers
- 2019
- [c19]Zhong Liu, Xi Tian, Xiaowen Chen, Yuanwu Lei, Man Liao:
Efficient Large-Scale 1D FFT Vectorization on Multi-Core Vector Accelerator. HPCC/SmartCity/DSS 2019: 484-491 - [c18]Sheng Ma, Libo Huang, Yuanwu Lei, Yang Guo, Zhiying Wang:
An Efficient Direct Memory Access (DMA) Controller for Scientific Computing Accelerators. ISCAS 2019: 1-5 - 2017
- [c17]Peng Qiao, Teng Li, Yong Dou, Yuanwu Lei, Hongbing Luo, Chi Jin:
Platform-Adaptive High-Throughput Surveillance Video Condensation on Heterogeneous Processor Clusters. APPT 2017: 1-13 - 2016
- [c16]Yuanxi Peng, Tingting He, Yuanwu Lei, Baozhou Zhu:
Single/Double Precision Floating-Point Division and Square Root Unit Based on SRT-8 Algorithm. NCCET 2016: 3-14 - [c15]Xiaowen Chen, Zhonghai Lu, Yuanwu Lei, Yaohua Wang, Shenggang Chen:
Multi-bit transient fault control for NoC links using 2D fault coding method. NOCS 2016: 1-8 - 2015
- [c14]Song Guo, Yong Dou, Yuanwu Lei, Qiang Wang, Fei Xia, Jianning Chen:
Designing Parallel Sparse Matrix Transposition Algorithm Using ELLPACK-R for GPUs. NCCET 2015: 61-68 - [c13]Yueqing Wang, Yong Dou, Song Guo, Yuanwu Lei, Baofeng Li, Qiang Wang:
Accelerating Molecular Dynamics Simulations on Heterogeneous Architecture. NCCET 2015: 118-132 - 2011
- [c12]Yuanwu Lei, Yong Dou, Song Guo, Jie Zhou:
FPGA Implementation of Variable-Precision Floating-Point Arithmetic. APPT 2011: 127-141 - [c11]Yuanwu Lei, Yong Dou, Jie Zhou, Sufeng Wang:
VPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point Arithmetic. FPL 2011: 252-257 - [c10]Yuanwu Lei, Yong Dou, Li Shen, Jie Zhou, Song Guo:
Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA. ICCD 2011: 219-225 - 2010
- [c9]Yong Dou, Yuanwu Lei, Guiming Wu, Song Guo, Jie Zhou, Li Shen:
FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing. ICS 2010: 325-336 - 2009
- [c8]Jie Zhou, Yong Dou, Jianxun Zhao, Fei Xia, Yuanwu Lei, Yuxing Tang:
A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA. APPT 2009: 110-122 - [c7]Guiming Wu, Yong Dou, Yuanwu Lei, Jie Zhou, Miao Wang, Jingfei Jiang:
A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs. FCCM 2009: 183-190 - [c6]Yong Dou, Jie Zhou, Xiaoyang Chen, Yuanwu Lei, Jinbo Xu:
FPGA accelerating three QR decomposition algorithms in the unified pipelined framework. FPL 2009: 410-416 - 2008
- [c5]Baofeng Li, Yong Dou, Yuanwu Lei:
Area and throughput trade-offs in design of arithmetic encoder for JPEG2000. APCCAS 2008: 316-319 - [c4]Jie Zhou, Yong Dou, Yuanwu Lei, Yazhuo Dong:
Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. ARC 2008: 254-259 - [c3]Jie Zhou, Yong Dou, Yuanwu Lei, Jinbo Xu, Yazhuo Dong:
Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. HPCC 2008: 182-189 - [c2]Jie Zhou, Yazhuo Dong, Yong Dou, Yuanwu Lei:
Dynamic Configurable Floating-Point FFT Pipelines and Hybrid-Mode CORDIC on FPGA. ICESS 2008: 616-620 - 2007
- [c1]Yong Dou, Jie Zhou, Yuanwu Lei, Xingming Zhou:
FPGA SAR Processor with Window Memory Accesses. ASAP 2007: 95-100
Coauthor Index
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