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Xiaowen Chen
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2020 – today
- 2024
- [j35]Minhui Ji, Jiayuan Wang, Liyuan Yang, Xinmiao Zhang, Yueguo Hu, Qingfa Du, Jiafei Hu, Weicheng Qiu, Junping Peng, Xiaowen Chen, Yanxiang Luo, Bin Fang, Peisen Li, Mengchun Pan:
Spin-Transfer-Torque Magnetic Tunnel Junction Nonlinear In-Sensor Computing Synapse for Improving the Performance of the Feedforward Neural Network. Adv. Intell. Syst. 6(6) (2024) - [j34]Xiaowen Chen, Guanci Yang, Yang Li, Qingsheng Xie, Xiang Liu:
Heart rate measurement based on spatiotemporal features of facial key points. Biomed. Signal Process. Control. 96: 106650 (2024) - [j33]Xiaowen Chen, Naiang Wang, Simin Peng, Nan Meng, Haoyun Lv:
Analysis of Spatiotemporal Dynamics of Land Desertification in Qilian Mountain National Park Based on Google Earth Engine. ISPRS Int. J. Geo Inf. 13(4): 117 (2024) - [c36]Yijing Peng, Yang Zhang, Qijin Zhu, Yang Guo, Xiaowen Chen:
ELSeM: An Efficient and Lightweight Security Mechanism for DSP. ITC-Asia 2024: 1-6 - [c35]Ta Tan, Xiaowen Chen, Chen Li, Jianzhuang Lu:
Load balancing-oriented fault-tolerant NoC design. ITC-Asia 2024: 1-6 - 2022
- [j32]Edward D. Lee, Xiaowen Chen, Bryan C. Daniels:
Discovering sparse control strategies in neural activity. PLoS Comput. Biol. 18(5) (2022) - [j31]Mingjie Wei, Yunping Zhao, Xiaowen Chen, Chen Li, Jianzhuang Lu:
Towards Convolutional Neural Network Acceleration and Compression Based on Simonk-Means. Sensors 22(11): 4298 (2022) - [j30]Hanyan Liu, Xiaowen Chen, Yunping Zhao, Chen Li, Jianzhuang Lu:
TTQR: A Traffic- and Thermal-Aware Q-Routing for 3D Network-on-Chip. Sensors 22(22): 8721 (2022) - [c34]Wencai Gao, Xiaowen Chen, Chen Li, Jianzhuang Lu, Hanyan Liu:
HCER: A High Cost-Effectiveness Multi-Bit Fault-Tolerant NoC Router. HPCC/DSS/SmartCity/DependSys 2022: 1241-1248 - [c33]Zhen Gao, Xiaowen Chen, Jingning Xu, Rongjie Yu, Jiaqi Zong:
A Comprehensive Vision-Based Model for Commercial Truck Driver Fatigue Detection. ICONIP (3) 2022: 182-193 - [c32]Mingjie Wei, Yunping Zhao, Jianzhuang Lu, Xiaowen Chen, Chen Li, Zerun Li:
Convolutional Neural Network Accelerator for Compression Based on Simon k-means. IJCNN 2022: 1-7 - 2021
- [j29]Jie Wu, Li Zhang, Qian Song, Lei Yu, Shuyuan Wang, Bo Zhang, Weida Wang, Peng Xia, Xiaowen Chen, Yun Xiao, Chaohan Xu:
Systematical identification of cell-specificity of CTCF-gene binding based on epigenetic modifications. Briefings Bioinform. 22(1): 589-600 (2021) - [j28]Guoshi Wang, Ying Liu, Xiaowen Chen, Qing Yan, Haibin Sui, Chao Ma, Junfei Zhang:
Power transformer fault diagnosis system based on Internet of Things. EURASIP J. Wirel. Commun. Netw. 2021(1): 21 (2021) - [j27]Zenggang Xiong, Zhiwen Tang, Xiaowen Chen, Xue-min Zhang, Kaibin Zhang, Conghuan Ye:
Research on Image Retrieval Algorithm Based on Combination of Color and Shape Features. J. Signal Process. Syst. 93(2-3): 139-146 (2021) - [c31]Yuekai Zhao, Jianzhuang Lu, Xiaowen Chen:
Accelerating Depthwise Separable Convolutions with Vector Processor. ICANN (2) 2021: 145-156 - [c30]Yuekai Zhao, Jianzhuang Lu, Xiaowen Chen:
Vectorized Winograd's algorithm for Convolution Neural networks. ISPA/BDCloud/SocialCom/SustainCom 2021: 715-722 - 2020
- [j26]Jun Wang, Xiaowen Chen, Funan He, Xiao Song, Shu Huang, Wucheng Yue, Yipei Chen, Zhixi Su, Chenghui Wang:
Global Analysis of Gene Expression Profiles Provides Novel Insights into the Development and Evolution of the Large Crustacean Eriocheir sinensis. Genom. Proteom. Bioinform. 18(4): 443-454 (2020) - [j25]Yunping Zhao, Jianzhuang Lu, Xiaowen Chen:
An Accelerator Design Using a MTCA Decomposition Algorithm for CNNs. Sensors 20(19): 5558 (2020) - [c29]Yunping Zhao, Jianzhuang Lu, Xiaowen Chen:
A Design of GEMM Parallel Computing Accelerator Based on Vector SIMD Technology. ICCTA 2020: 122-128 - [c28]Xiaowen Chen:
Middle-School Chinese Students Adjusting to Western Approaches to Teaching and Learning: A Study of Students' Intercultural Competence. ICLS 2020 - [c27]Yunping Zhao, Xiaowen Chen, Rui Xu, Jinhui Wei, Jianzhuang Lu, Bo Yuan:
A Research and Design of Lightweight Convolutional Neural Networks Accelerator Based on Systolic Array Structure. ICRAI 2020: 241-247 - [c26]Yaohua Wang, Xiaowen Chen, Xiao Hu:
Associative Thread Compaction for Efficient Control Flow Handling in GPGPUs. ISVLSI 2020: 228-233
2010 – 2019
- 2019
- [c25]Zhong Liu, Xi Tian, Xiaowen Chen, Yuanwu Lei, Man Liao:
Efficient Large-Scale 1D FFT Vectorization on Multi-Core Vector Accelerator. HPCC/SmartCity/DSS 2019: 484-491 - [c24]Zicong Wang, Xiaowen Chen, Chen Li, Yang Guo, Man Liao, Zhong Liu:
Load-Balanced Link Distribution in Mesh-Based Many-Core Systems. HPCC/SmartCity/DSS 2019: 1028-1034 - 2018
- [j24]Zicong Wang, Xiaowen Chen, Zhonghai Lu, Yang Guo:
Cache Access Fairness in 3D Mesh-Based NUCA. IEEE Access 6: 42984-42996 (2018) - [j23]Zicong Wang, Xiaowen Chen, Junyang Zhang, Yang Guo:
VP-Router: On balancing the traffic load in on-chip networks. IEICE Electron. Express 15(22): 20180883 (2018) - [j22]Xiaowen Chen, Yuanwu Lei, Zhonghai Lu, Shuming Chen:
A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1953-1966 (2018) - 2017
- [j21]Yang Li, Hua Cai, Xiaowen Chen:
Impact of adjacent transistors on the SEU sensitivity of DICE flip-flop. IEICE Electron. Express 14(5): 20170027 (2017) - [j20]Ding Deng, Xiaowen Chen, Yang Guo:
A novel power-efficient IC test scheme. IEICE Electron. Express 14(13): 20170462 (2017) - [j19]Xiaowen Chen, Zhonghai Lu, Sheng Liu, Shuming Chen:
Round-trip DRAM Access Fairness in 3D NoC-based Many-core Systems. ACM Trans. Embed. Comput. Syst. 16(5s): 162:1-162:21 (2017) - [c23]Ze He, Xiaowen Chen:
Design and implementation of high-speed configurable ECC co-processor. ASICON 2017: 734-737 - [c22]Zicong Wang, Xiaowen Chen, Chen Li, Yang Guo:
Fairness-Oriented and Location-Aware NUCA for Many-Core SoC. NOCS 2017: 13:1-13:8 - [c21]Zicong Wang, Xiaowen Chen, Chen Li, Yang Guo:
Fairness-oriented switch allocation for networks-on-chip. SoCC 2017: 304-309 - 2016
- [j18]Yaohua Wang, Dong Wang, Shuming Chen, Zonglin Liu, Shenggang Chen, Xiaowen Chen, Xu Zhou:
Iteration Interleaving-Based SIMD Lane Partition. ACM Trans. Archit. Code Optim. 12(4): 58:1-58:18 (2016) - [c20]Yaohua Wang, Xiaowen Chen, Dong Wang, Sheng Liu:
Dynamic Per-Warp Reconvergence Stack for Efficient Control Flow Handling in GPUs. ISVLSI 2016: 176-181 - [c19]Xiaowen Chen, Zhonghai Lu, Yuanwu Lei, Yaohua Wang, Shenggang Chen:
Multi-bit transient fault control for NoC links using 2D fault coding method. NOCS 2016: 1-8 - 2015
- [j17]Yingli Lv, Shuyuan Wang, Fanlin Meng, Lei Yang, Zhifeng Wang, Jing Wang, Xiaowen Chen, Wei Jiang, Yixue Li, Xia Li:
Identifying novel associations between small molecules and miRNAs based on integrated molecular networks. Bioinform. 31(22): 3638-3644 (2015) - [j16]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo, Shenggang Chen, Hu Chen:
Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications. J. Electr. Comput. Eng. 2015: 902591:1-902591:20 (2015) - [j15]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo, Shenggang Chen, Hu Chen, Man Liao:
Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips. J. Softw. 10(2): 142-161 (2015) - [c18]Xiaowen Chen, Zhonghai Lu, Yang Li, Axel Jantsch, Xueqian Zhao, Shuming Chen, Yang Guo, Zonglin Liu, Jianzhuang Lu, Jianghua Wan, Shuwei Sun, Shenggang Chen, Hu Chen:
Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs. ISVLSI 2015: 398-403 - 2014
- [j14]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo, Hengzhu Liu:
Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs. IEICE Electron. Express 11(18): 20140542 (2014) - [j13]Yang Li, Xiaowen Chen, Xiaohui Zhao, Yong Yang, Hengzhu Liu:
Round-trip latency prediction for memory access fairness in mesh-based many-core architectures. IEICE Electron. Express 11(24): 20141027 (2014) - [j12]Wei Zhang, Shujie Lyu, Yuliang Zhu, Xiaowen Chen:
A Coupled Model of the 1D River Network and 3D Estuary Based on Hydrodynamics and Suspended Sediment Simulation. J. Appl. Math. 2014: 798579:1-798579:13 (2014) - [j11]Wei Zhang, Qiong Jia, Xiaowen Chen:
Numerical Simulation of Flow and Suspended Sediment Transport in the Distributary Channel Networks. J. Appl. Math. 2014: 948731:1-948731:9 (2014) - 2013
- [j10]Wei Jiang, Yan Zhang, Fanlin Meng, Baofeng Lian, Xiaowen Chen, Xuexin Yu, Enyu Dai, Shuyuan Wang, Xinyi Liu, Xiang Li, Lihong Wang, Xia Li:
Identification of active transcription factor and miRNA regulatory pathways in Alzheimer's disease. Bioinform. 29(20): 2596-2602 (2013) - [j9]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Shenggang Chen, Huitao Gu:
Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property. Comput. Electr. Eng. 39(2): 596-612 (2013) - 2012
- [j8]Xia Li, Wei Jiang, Wei Li, Baofeng Lian, Shuyuan Wang, Mingzhi Liao, Xiaowen Chen, Yanqiu Wang, Yingli Lv, Shiyuan Wang, Lei Yang:
Dissection of human MiRNA regulatory influence to subpathway. Briefings Bioinform. 13(2): 175-186 (2012) - [j7]Yaohua Wang, Shuming Chen, Kai Zhang, Jianghua Wan, Xiaowen Chen, Hu Chen, Haibo Wang:
Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures. IEEE Comput. Archit. Lett. 11(2): 37-40 (2012) - [j6]Kai Zhang, Shuming Chen, Hu Chen, Yaohua Wang, Xiaowen Chen, Sheng Liu, Wei Liu:
CMRF: a Configurable Matrix Register File for accelerating matrix operations on SIMD processors. IEICE Electron. Express 9(4): 283-289 (2012) - [c17]Yaohua Wang, Shuming Chen, Kai Zhang, Hu Chen, Xiaowen Chen:
Architecture Design Trade-offs among VLIW SIMD and Multi-core Schemes. IPDPS Workshops 2012: 1649-1658 - [c16]Xin Zhang, Hengjian Tong, Xiaowen Chen:
Multi-scale Segmentation Algorithm Parameters Optimization Based on Evolutionary Computation. ISICA 2012: 347-358 - 2011
- [j5]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Hai Liu:
Cooperative communication based barrier synchronization in on-chip mesh architectures. IEICE Electron. Express 8(22): 1856-1862 (2011) - [j4]Xiaowen Chen, Shuming Chen, Zhonghai Lu, Axel Jantsch:
Hybrid Distributed Shared Memory Space in Multi-core Processors. J. Softw. 6(12): 2369-2378 (2011) - [c15]Shuming Chen, Xiaowen Chen, Yi Xu, Jianghua Wan, Jianzhuang Lu, Xiangyuan Liu, Shenggang Chen:
Design and chip implementation of a heterogeneous multi-core DSP. ASP-DAC 2011: 91-92 - [c14]Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch:
Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems. ASP-DAC 2011: 154-159 - [c13]Abdul Naeem, Axel Jantsch, Xiaowen Chen, Zhonghai Lu:
Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems. DSD 2011: 47-54 - [c12]Xiaowen Chen, Shuming Chen:
DSBS: Distributed and Scalable Barrier Synchronization in Many-Core Network-on-Chips. TrustCom 2011: 1030-1037 - 2010
- [j3]Shuming Chen, Jianghua Wan, Jianzhuang Lu, Zhong Liu, Hai-Yan Sun, Yong-Jie Sun, Hengzhu Liu, Xiang-Yuan Liu, Zhentao Li, Yi Xu, Xiaowen Chen:
YHFT-QDSP: High-Performance Heterogeneous Multi-Core DSP. J. Comput. Sci. Technol. 25(2): 214-224 (2010) - [c11]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen:
Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller. DATE 2010: 39-44 - [c10]Shenggang Chen, Shuming Chen, Huitao Gu, Hu Chen, Yaming Yin, Xiaowen Chen, Shuwei Sun, Sheng Liu, Yaohua Wang:
Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform. HPCC 2010: 465-470 - [c9]Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch:
Scalability of weak consistency in NoC based multicore architectures. ISCAS 2010: 3497-3500 - [c8]Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrjä, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, Philippe Martin:
The MOSART Mapping Optimization for Multi-Core ARchiTectures. ISVLSI (Selected papers) 2010: 181-195 - [c7]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Jianzhuang Lu, Hucheng Wu:
Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique. ISVLSI 2010: 462-463 - [c6]Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrjä, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, Philippe Martin:
Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach. ISVLSI 2010: 518-523 - [c5]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen:
Run-Time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips. PAAP 2010: 39-46 - [c4]Huitao Gu, Shuming Chen, Shuwei Sun, Shenggang Chen, Xiaowen Chen:
Multiple Search Centers Based Fast Motion Estimation Algorithm for H.264/AVC. PDCAT 2010: 346-350 - [c3]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen:
Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory. SoCC 2010: 467-472
2000 – 2009
- 2009
- [j2]Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch:
Scalability of relaxed consistency models in NoC based multicore architectures. SIGARCH Comput. Archit. News 37(5): 8-15 (2009) - 2008
- [j1]Jiangshe Zhang, Yuqian Yang, Xiaowen Chen, Chenghu Zhou:
Enhanced piecewise regression based on deterministic annealing. Sci. China Ser. F Inf. Sci. 51(8): 1025-1038 (2008) - 2007
- [c2]Dong Wang, Xiaowen Chen, Shuming Chen, Xing Fang, Shuwei Sun:
FCC-SDP: A Fast Close-Coupled Shared Data Pool for Multi-core DSPs. Asia-Pacific Computer Systems Architecture Conference 2007: 80-89 - 2001
- [c1]Xiaowen Chen, Tim Wahls:
A graphical user interface for executing formal specifications. SAC 2001: 648-652
Coauthor Index
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last updated on 2024-10-15 20:47 CEST by the dblp team
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