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2020 – today
- 2023
[j15]Hong-Yi Huang, Jen-Chieh Liu
, Fu-Chien Tsai, Kun-Hua Lee, Kun-Yuan Chen:
A 12-Phase and 5-GHz PLL with a Subfeedback Loop Technique. Circuits Syst. Signal Process. 42(4): 1873-1892 (2023)- 2021
- [j14]Jen-Chieh Liu, Yu-Ping Li:
A Low Supply Voltage All-Digital Phase-Locked Loop With a Bootstrapped and Forward Interpolation Digitally Controlled Oscillator. IEEE Access 9: 39717-39726 (2021)
2010 – 2019
- 2018
- [j13]Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Chi-Yang Chang:
Low supply voltage and multiphase all-digital crystal-less clock generator. IET Circuits Devices Syst. 12(6): 720-725 (2018) - [j12]Jen-Chieh Liu, Tzu-Yun Wu, Tuo-Hung Hou:
Optimizing Incremental Step Pulse Programming for RRAM Through Device-Circuit Co-Design. IEEE Trans. Circuits Syst. II Express Briefs 65-II(5): 617-621 (2018) - [j11]Yo-Hao Tu, Kuo-Hsing Cheng, Man-Ju Lee, Jen-Chieh Liu:
A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(7): 2097-2108 (2018) - [j10]Jen-Chieh Liu, Chao-Jen Huang, Pei-Ying Lee:
A High-Accuracy Programmable Pulse Generator With a 10-ps Timing Resolution. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 621-629 (2018) - 2017
- [j9]Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan, Jen-Chieh Liu, Yu Lee:
A 8 Phases 192MHz Crystal-Less Clock Generator with PVT Calibration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(1): 275-282 (2017) - 2016
- [j8]Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, Chang-Chien Hu:
A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC. IEICE Electron. Express 13(2): 20150950 (2016) - [j7]Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng:
Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture. IEICE Trans. Electron. 99-C(6): 655-658 (2016) - [j6]Jen-Chieh Liu, Pei-Ying Lee:
A Low Power Pulse Generator for Test Platform Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1415-1416 (2016) - [c11]Yo-Hao Tu, Kuo-Hsing Cheng, Wei-Ren Wang, Jen-Chieh Liu, Hong-Yi Huang:
A chaotically injected timing technique for ring-based oscillators. DDECS 2016: 31-34 - 2015
- [c10]Hong-Yi Huang, Jen-Chieh Liu, Pei-Ying Lee, Kun-Yuan Chen, Jin-Sheng Chen, Kuo-Hsing Cheng, Tzuen-Hsi Huang, Ching-Hsing Luo, Jin-Chern Chiou:
PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing. DDECS 2015: 125-128 - 2014
- [j5]Kuo-Hsing Cheng, Cheng-Liang Hung, Cihun-Siyong Alex Gong, Jen-Chieh Liu, Bo-Qian Jiang, Shi-Yang Sun:
A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes. IEEE Trans. Circuits Syst. II Express Briefs 61-II(8): 559-563 (2014) - [c9]Hong-Yi Huang, Jen-Chieh Liu, Shi-Jia Sun, Cheng-Hao Fu, Kuo-Hsing Cheng:
A 64-MHz∼640-MHz 64-phase clock generator. DDECS 2014: 51-54 - [c8]Jen-Chieh Liu, Huan-Ke Chiu, Jia-Hung Peng, Yuan-Hua Chu, Hong-Yi Huang:
A radio-controlled receiver for clocks/watches and alarm applications. ISCAS 2014: 2672-2675 - 2012
- [j4]Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang:
A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 888-892 (2012) - [c7]Chih-Ping Cheng, Jen-Chieh Liu, Kuo-Hsing Cheng:
Auto-calibration techniques in built-in jitter measurement circuit. DDECS 2012: 248-249 - 2011
- [j3]Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang, Yu-Liang Li, Yong-Jhen Jhu:
A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler. IEEE Trans. Circuits Syst. II Express Briefs 58-II(8): 492-496 (2011) - [j2]Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Hsiang Chen, Jen-Chieh Liu:
A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit. IEEE Trans. Very Large Scale Integr. Syst. 19(7): 1218-1228 (2011) - [j1]Kuo-Hsing Cheng, Jen-Chieh Liu, Chih-Yu Chang, Shu-Yu Jiang, Kai-Wei Hong:
Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1325-1335 (2011) - [c6]Tzu-Chi Huang, Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng, Ching-Hsing Luo:
All digital phase-locked loop using active inductor oscillator and novel locking algorithm. ISCAS 2011: 486-489 - 2010
- [c5]Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang:
A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. DDECS 2010: 285-288 - [c4]Kai-Wei Hong, Kuo-Hsing Cheng, Chi-Hsiang Chen, Jen-Chieh Liu, Chien-Cheng Chen:
A loading effect insensitive and high precision clock synchronization circuit. ESSCIRC 2010: 514-517
2000 – 2009
- 2009
- [c3]Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng:
0.5V 160-MHz 260uW all digital phase-locked loop. DDECS 2009: 186-193 - 2007
- [c2]Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng:
All-Digital PLL Using Pulse-Based DCO. ICECS 2007: 1268-1271 - 2006
- [c1]Hong-Yi Huang, Bo-Ruei Wang, Jen-Chieh Liu:
High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit. ISCAS 2006
Coauthor Index
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