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2020 – today
- 2021
[c11]Ming Yang, Shayan Shahramian, Henry Wong, Peter Krotnev, Anthony Chan Carusone:
Pre-FEC and Post-FEC BER as Criteria for Optimizing Wireline Transceivers. ISCAS 2021: 1-5- [c10]Marc-Andre LaCroix, Euhan Chong, Weilun Shen, Ehud Nir, Faisal Ahmed Musa, Haitao Mei, Mohammad-Mahdi Mohsenpour, Semyon Lebedev, Babak Zamanlooy, Carlos Carvalho, Qian Xin, Dmitry Petrov, Henry Wong, Huong Ho, Yang Xu, Sina Naderi Shahi, Peter Krotnev, Chris Feist, Howard Huang, Davide Tonietto:
8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2. ISSCC 2021: 132-134 - [c9]Henry Wong, Xiaolong Zhang, Tuopu Wen, Mengmeng Yang, Kun Jiang
, Diange Yang:
HD-Map Aided LiDAR-INS Extrinsic Calibration. ITSC 2021: 3136-3143 - 2020
- [j6]Taohua Zhou, Mengmeng Yang, Kun Jiang, Henry Wong, Diange Yang:
MMW Radar-Based Technologies in Autonomous Driving: A Review. Sensors 20(24): 7283 (2020) - [j5]Ming Yang, Shayan Shahramian, Hossein Shakiba, Henry Wong, Peter Krotnev, Anthony Chan Carusone:
Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 284-297 (2020)
2010 – 2019
- 2019
- [c8]Marc-Andre LaCroix, Henry Wong, Yun Hua Liu, Huong Ho, Semyon Lebedev, Petar Krotnev, Dorin Alexandru Nicolescu, Dmitry Petrov, Carlos Carvalho, Stephen Alie, Euhan Chong, Faisal Ahmed Musa, Davide Tonietto:
A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss. ISSCC 2019: 114-116 - 2018
- [j4]Henry Wong, Vaughn Betz, Jonathan Rose:
High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors. ACM Trans. Reconfigurable Technol. Syst. 11(1): 1:1-1:22 (2018) - 2016
- [j3]Henry Wong, Vaughn Betz, Jonathan Rose:
Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System. ACM Trans. Reconfigurable Technol. Syst. 10(1): 7:1-7:22 (2016) - [c7]Henry Wong, Vaughn Betz, Jonathan Rose:
High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors. FCCM 2016: 9-16 - [c6]Henry Wong, Sana Ullah Qaisar, Michael J. Ryan:
Assessing design dependencies in modular systems. SysCon 2016: 1-8 - 2014
- [j2]Henry Wong, Vaughn Betz, Jonathan Rose:
Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2067-2080 (2014) - 2013
- [c5]Henry Wong, Vaughn Betz, Jonathan Rose:
Efficient methods for out-of-order load/store execution for high-performance soft processors. FPT 2013: 442-445 - 2011
- [j1]Jonathan G. Koomey, Stephen Berard, Marla Sanchez, Henry Wong:
Implications of Historical Trends in the Electrical Efficiency of Computing. IEEE Ann. Hist. Comput. 33(3): 46-54 (2011) - [c4]Henry Wong, Vaughn Betz, Jonathan Rose:
Comparing FPGA vs. custom cmos and the impact on processor microarchitecture. FPGA 2011: 5-14 - 2010
- [c3]Henry Wong, Misel-Myrto Papadopoulou, Maryam Sadooghi-Alvandi, Andreas Moshovos:
Demystifying GPU microarchitecture through microbenchmarking. ISPASS 2010: 235-246
2000 – 2009
- 2009
- [c2]Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, Henry Wong, Tor M. Aamodt:
Analyzing CUDA workloads using a detailed GPU simulator. ISPASS 2009: 163-174 - 2008
- [c1]Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang:
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. PACT 2008: 52-61 - 2004
- [b3]Scott Oaks, Henry Wong:
Java threads - understanding and mastering concurrent programming: covers J2SE 5.o (3. ed.). O'Reilly 2004, ISBN 978-0-596-00782-9, pp. I-XVI, 1-340 - 2000
- [b2]Scott Oaks, Henry Wong:
Jini in a nutshell - a desktop quick reference. O'Reilly 2000, ISBN 978-1-56592-759-9, pp. I-XIII, 1-400
1990 – 1999
- 1999
- [b1]Scott Oaks, Henry Wong:
Java threads - Java 2 (2. ed.). O'Reilly 1999, ISBN 978-1-56592-418-5, pp. I-XVI, 1-358
Coauthor Index
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