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ORCIDMarisa López-Vallejo
Marisa Luisa López-Vallejo – María Luisa López Vallejo
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2020 – today
- 2025
[j31]Samuel López Asunción
, Jorge Gonzalez-Lopez, Carlos Garcia de la Cueva, Marisa López-Vallejo, Jesús Grajal:
Design and Implementation of a Real-Time Low-Latency Automatic Modulation Classifier. IEEE Trans. Instrum. Meas. 74: 1-12 (2025)- 2024
- [c49]Javier De Mena Pacheco, Borja Gutiérrez De Cabiedes, Amadeo de Gracia Herranz, Marisa López-Vallejo:
A Lightweight Analog RFID Front-End for Interfacing Sensors. DCIS 2024: 1-6 - [c48]Oliver Schrape, Anselm Breitenreiter, Li Lu, Marko S. Andjelkovic, Ernesto Pun-Garcia, Marisa López-Vallejo, Milos Krstic:
Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flop with Self-Correction. NorCAS 2024: 1-4 - 2023
- [j30]Víctor Manuel Bautista, Mario Garrido, Marisa López-Vallejo:
Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond. IEEE Trans. Circuits Syst. I Regul. Pap. 70(10): 3992-4003 (2023) - [c47]Alba Páez-Montoro, Javier De Mena Pacheco, Marisa López-Vallejo, Celia López-Ongil, Susana Patón:
Ring Oscillator Circuits in Flexible aIGZO Technology for Biosignal Acquisition. DCIS 2023: 1-6 - 2022
- [j29]Hernan Aparicio, Pablo Ituero, Marisa López-Vallejo:
Reference-free power supply monitor with enhanced robustness against process and temperature variations. Integr. 82: 127-135 (2022) - [j28]Miguel Molina, Javier Mendez, Diego Pedro Morales, Encarnación Castillo, Marisa López-Vallejo, Manuel Pegalajar:
Power-Efficient Implementation of Ternary Neural Networks in Edge Devices. IEEE Internet Things J. 9(20): 20111-20121 (2022) - [c46]Samuel López Asunción, Pablo Ituero, Marisa López-Vallejo, Jesús Grajal:
Data Synchronization in Non-Uniform Latency Custom DSP Designs. DCIS 2022: 1-6 - 2021
- [j27]Amadeo de Gracia Herranz, Marisa López-Vallejo:
Time to Digital Sensing for Multilevel RRAM Cells. IEEE Access 9: 160216-160223 (2021) - [c45]Javier De Mena Pacheco, Marisa López-Vallejo:
A 65nm Current and Voltage Reference with Improved Line Regulation for Implantable Biosensors. DCIS 2021: 1-5 - 2020
- [j26]Amadeo de Gracia Herranz, Marisa López-Vallejo:
Time-domain writing architecture for multilevel RRAM cells resilient to temperature and process variations. Integr. 75: 141-149 (2020) - [c44]Samuel López Asunción, Marisa López-Vallejo, Jesús Grajal:
Algorithm-Architecture Optimization for Linear and Quadratic Regression on Reconfigurable Platforms. DCIS 2020: 1-6 - [c43]Asghar Bahramali, Marisa López-Vallejo, Carlos A. López-Barrio:
An ultra-low power deep sub-micron fast start-up circuit with added line regulation. DCIS 2020: 1-5
2010 – 2019
- 2019
- [j25]Asghar Bahramali, Marisa López-Vallejo:
A low power RFID based energy harvesting temperature resilient CMOS-only reference voltage. Integr. 67: 155-161 (2019) - [c42]Asghar Bahramali, Marisa López-Vallejo, Carlos A. López-Barrio:
A 365mV, 13nW CMOS-only energy harvested reference voltage for RFID applications in 40nm technology. DCIS 2019: 1-6 - [c41]Amadeo de Gracia Herranz, Marisa López-Vallejo:
Temperature-aware writing architecture for multilevel memristive cells. PATMOS 2019: 57-62 - 2018
- [j24]Fernando García-Redondo, Marisa López-Vallejo:
Auto-Erasable RRAM Architecture Secured Against Physical and Firmware Attacks. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(5): 1581-1590 (2018) - [j23]Mario Garrido, Marisa Luisa López-Vallejo, Sau-Gee Chen:
Guest Editorial: Special Section on Fast Fourier Transform (FFT) Hardware Implementations. J. Signal Process. Syst. 90(11): 1581-1582 (2018) - [c40]Daniel Fortun, Carlos Garcia de la Cueva, Jesús Grajal, Marisa López-Vallejo, Carlos A. López-Barrio:
Performance-oriented Implementation of Hilbert Filters on FPGAs. DCIS 2018: 1-6 - [c39]Asghar Bahramali, Marisa López-Vallejo:
A Temperature Variation Tolerant CMOS-Only Voltage Reference for RFID Applications. PATMOS 2018: 62-67 - 2017
- [j22]Mario Garrido, Miguel Angel Sánchez, María Luisa López Vallejo, Jesús Grajal:
A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 375-379 (2017) - [j21]Fernando García-Redondo, Pablo Royer, Marisa López-Vallejo, Hernan Aparicio, Pablo Ituero, Carlos A. López-Barrio:
Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1224-1235 (2017) - [c38]Fernando García-Redondo, Marisa López-Vallejo, Carlos A. López-Barrio:
Advanced integration of variability and degradation in RRAM SPICE compact models. SMACD 2017: 1-4 - 2016
- [j20]Fernando García-Redondo, Robert P. Gowers, Albert Crespo-Yepes, Marisa López-Vallejo, Liudi Jiang:
SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8): 1255-1264 (2016) - [j19]Jose M. Nadal-Serrano, Marisa López-Vallejo:
A Performance Study of CUDA UVM versus Manual Optimizations in a Real-World Setup: Application to a Monte Carlo Wave-Particle Event-Based Interaction Model. IEEE Trans. Parallel Distributed Syst. 27(6): 1579-1588 (2016) - [c37]Javier Agustin, Marisa Luisa López-Vallejo:
A temperature-independent PUF with a configurable duty cycle of CMOS ring oscillators. ISCAS 2016: 2471-2474 - [c36]Fernando García-Redondo, Marisa López-Vallejo, Hernan Aparicio, Pablo Ituero:
Reliable design methodology: The combined effect of radiation, variability and temperature. SMACD 2016: 1-4 - 2015
- [j18]Victor Iglesias, Jesús Grajal, Pablo Royer, Miguel A. Sánchez Marcos, Marisa López-Vallejo, Omar A. Yeste Ojeda:
Real-time low-complexity automatic modulation classifier for pulsed radar signals. IEEE Trans. Aerosp. Electron. Syst. 51(1): 108-126 (2015) - [j17]Javier Agustin, Marisa López-Vallejo:
An In-Depth Analysis of Ring Oscillators: Exploiting Their Configurable Duty-Cycle. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(10): 2485-2494 (2015) - [j16]Victor Iglesias, Jesús Grajal, Miguel A. Sánchez Marcos, Marisa López-Vallejo:
Implementation of a Real-Time Spectrum Analyzer on FPGA Platforms. IEEE Trans. Instrum. Meas. 64(2): 338-355 (2015) - [c35]Ignacio Herrera-Alzu, Marisa López-Vallejo, C. Gil Soriano:
A Dual-Layer Fault Manager for systems based on Xilinx Virtex FPGAs. DFTS 2015: 72-75 - [c34]Fernando García-Redondo, Marisa López-Vallejo, Pablo Ituero:
A thermal adaptive scheme for reliable write operation on RRAM based architectures. ICCD 2015: 367-374 - [c33]Pablo Royer, Fernando García-Redondo, Marisa López-Vallejo:
Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm. NANOARCH 2015: 112-117 - 2014
- [j15]Carlos Gómez Osuna, Pablo Ituero, Marisa López-Vallejo:
A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs). Sensors 14(1): 129-143 (2014) - 2013
- [j14]Pablo Ituero, Marisa López-Vallejo, Carlos A. López-Barrio:
A 0.0016 mm2 0.64 nJ Leakage-Based CMOS Temperature Sensor. Sensors 13(9): 12648-12662 (2013) - [j13]Florent de Dinechin, Pedro Echeverría, Marisa López-Vallejo, Bogdan Pasca:
Floating-Point Exponentiation Units for Reconfigurable Computing. ACM Trans. Reconfigurable Technol. Syst. 6(1): 4:1-4:15 (2013) - [j12]Pedro Echeverría, Marisa López-Vallejo:
High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator. J. Signal Process. Syst. 71(2): 105-109 (2013) - [c32]Carlos Benito, Pablo Ituero, Marisa López-Vallejo:
A Low-Area Reference-Free Power Supply Sensor. DSD 2013: 728-733 - [c31]Pablo Royer, Marisa López-Vallejo:
A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm node. ACM Great Lakes Symposium on VLSI 2013: 37-42 - 2012
- [c30]Miguel Angel Sánchez, Marisa López-Vallejo, Carlos Angel Iglesias, Carlos A. López-Barrio:
Improving Hardware Reuse through XML-based Interface Encapsulation. ICECCS 2012: 49-56 - [c29]Carlos Gómez Osuna, Miguel A. Sánchez Marcos, Pablo Ituero, Marisa López-Vallejo:
A monitoring infrastructure for FPGA self-awareness and dynamic adaptation. ICECS 2012: 765-768 - [c28]Miguel Angel Sánchez, Marisa López-Vallejo, Carlos Angel Iglesias:
Hardware Reuse Improvement through the Domain Specific Language dHDL. ISPA 2012: 857-858 - 2011
- [j11]Pedro Echeverría, Marisa López-Vallejo:
Customizing floating-point units for FPGAs: Area-performance-standard trade-offs. Microprocess. Microsystems 35(6): 535-546 (2011) - [c27]Pablo Ituero, Marisa López-Vallejo, Miguel A. Sánchez Marcos, Carlos Gómez Osuna:
On-chip Monitoring: A Light-Weight Interconnection Network Approach. DSD 2011: 619-625 - [c26]Jesús Grajal, Omar A. Yeste Ojeda, Miguel Angel Sánchez, Mario Garrido, Marisa López-Vallejo:
Real time FPGA implementation of an automatic modulation classifier for electronic warfare applications. EUSIPCO 2011: 1514-1518 - [c25]Ignacio Herrera-Alzu, Marisa López-Vallejo:
Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs. PATMOS 2011: 133-142 - 2010
- [j10]José Luis Ayala, Cándido Méndez, Marisa López-Vallejo:
Thermal analysis and modeling of embedded processors. Comput. Electr. Eng. 36(1): 142-154 (2010)
2000 – 2009
- 2009
- [c24]Pedro Echeverría, Marisa López-Vallejo, Walter Bolognesi, Carlos A. López-Barrio:
Exploring performance-power trade-offs for look-up tables in SRAM-based FPGAs. ICECS 2009: 423-426 - [p3]José L. Ayala, Marisa López-Vallejo, Davide Bertozzi, Luca Benini:
SoC Communication Architectures: From Interconnection Buses to Packet-Switched NoCs. Embedded Systems Design and Verification 2009: 14 - 2008
- [j9]José Luis Ayala, Marisa López-Vallejo, Carlos A. López-Barrio, Alexander V. Veidenbaum:
A hardware mechanism to reduce the energy consumption of the register file of in-order architectures. Int. J. Embed. Syst. 3(4): 285-293 (2008) - [j8]David Atienza, Praveen Raghavan, José Luis Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo:
Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures. Integr. 41(1): 38-48 (2008) - [j7]Pedro Echeverría Aramendi, José L. Ayala, Marisa López-Vallejo:
Power Considerations in Banked CAMs: A Leakage Reduction Approach. VLSI Design 2008: 674259:1-674259:7 (2008) - [c23]Pedro Echeverría, David B. Thomas, Marisa López-Vallejo, Wayne Luk:
An FPGA run-time parameterisable Log-Normal Random Number Generator. ARC 2008: 219-230 - [c22]Miguel Angel Sánchez, Pedro Echeverría, Francisco Mansilla, Marisa López-Vallejo:
Designing Highly Parameterized Hardware using xHdl. FDL 2008: 78-83 - [c21]Angel Fernandez Herrero, Ignacio Elguezábal, Marisa López-Vallejo:
A Web-Based Environment Providing Remote Access To FPGA Platforms For Teaching Digital Hardware Design. e-Learning 2008: 161-165 - [c20]Ignacio Herrera-Alzu, Miguel Angel Sánchez, Marisa López-Vallejo, Pedro Echeverría:
Experimental methodology for power characterization of FPGAs. ICECS 2008: 582-585 - [c19]Pedro Echeverría, Marisa López-Vallejo, Jose María Pesquero:
Variance reduction techniques for Monte Carlo simulations. A parameterizable FPGA approach. ICECS 2008: 1296-1299 - 2007
- [j6]José L. Ayala, Marisa López-Vallejo, David Atienza, Praveen Raghavan, Francky Catthoor, Diederik Verkest:
Energy-aware compilation and hardware design for VLIW embedded systems. Int. J. Embed. Syst. 3(1/2): 73-82 (2007) - [c18]Pablo Ituero, Gorka Landaburu, Javier Del Ser, Marisa López-Vallejo, Pedro M. Crespo, Vicente Atxa, Jon Altuna:
Joint Source-Channel Decoding ASIP Architecture for Sensor Networks. ICESS 2007: 98-108 - [c17]Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo:
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors. ISCAS 2007: 121-124 - [c16]Pablo Ituero, José L. Ayala, Marisa López-Vallejo:
Leakage-based On-Chip Thermal Sensor for CMOS Technology. ISCAS 2007: 3327-3330 - [i2]José Luis Ayala, Anya Apavatjrut, David Atienza, Marisa López-Vallejo, Carlos A. López-Barrio:
Thermal Characterization and Thermal Management in Processor-Based Systems. Power-aware Computing Systems 2007 - 2006
- [c15]Pablo Ituero, Marisa López-Vallejo:
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding. ASAP 2006: 291-296 - [c14]Miguel A. Sánchez Marcos, Mario Garrido, Marisa López-Vallejo, Carlos A. López-Barrio:
Automated design space exploration of FPGA-based FFT architectures based on area and power estimation. FPT 2006: 127-134 - [c13]José Luis Ayala, Cándido Méndez, Marisa López-Vallejo:
Analysis of the Thermal Impact of Source-Code Transformations in Embedded-Processors. ICECS 2006: 866-869 - [c12]Pedro Echeverría, José Luis Ayala, Marisa López-Vallejo:
Leakage Energy Reduction in Banked Content Addressable Memories. ICECS 2006: 1196-1199 - [c11]David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo:
Compiler-Driven Leakage Energy Reduction in Banked Register Files. PATMOS 2006: 107-116 - [c10]Cándido Méndez, José Luis Ayala, Marisa López-Vallejo:
Target Independent Thermal Modeling for Embedded Processors. IES 2006: 1-9 - 2005
- [j5]José Luis Ayala, Marisa López-Vallejo:
Integrating functional and power simulation in embedded systems design. J. Embed. Comput. 1(3): 325-340 (2005) - [r1]Davide Bertozzi, Luca Benini, Marisa López-Vallejo, José L. Ayala:
State-of-the-Art SoC Communication Architectures. Embedded Systems Handbook 2005 - [i1]José Luis Ayala, Marisa López-Vallejo:
Compiler-Driven Power Optimizations in the Register File of Processor-Based Systems. Power-aware Computing Systems 2005 - 2004
- [c9]Marcos M. A. Sanchez, Fernandez Herrero, Marisa López-Vallejo:
Improving IP core reuse through the application of the meta-language xHDL. FDL 2004: 493-505 - 2003
- [j4]José L. Ayala, Alexander V. Veidenbaum, Marisa Luisa López-Vallejo:
Power-Aware Compilation for Register File Energy Reduction. Int. J. Parallel Program. 31(6): 451-467 (2003) - [j3]Marisa Luisa López-Vallejo, Juan Carlos López:
On the hardware-software partitioning problem: System modeling and partitioning techniques. ACM Trans. Design Autom. Electr. Syst. 8(3): 269-297 (2003) - [c8]José L. Ayala, Marisa Luisa López-Vallejo, Alexander V. Veidenbaum, Carlos A. Lopez:
Energy Aware Register File Implementation through Instruction Predecode. ASAP 2003: 86-96 - [c7]Antonio G. Lomeña, Marisa Luisa López-Vallejo, Yosinori Watanabe, Alex Kondratyev:
An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling. DATE 2003: 10428-10435 - [c6]José L. Ayala, Marisa Luisa López-Vallejo:
A Unified Framework for Power-Aware Design of Embedded Systems. PATMOS 2003: 239-248 - [p2]Antonio G. Lomeña, Marisa López-Vallejo, Yosinori Watanabe, Alex Kondratyev:
State Space Compression in History Driven Quasi-Static Scheduling. Embedded Software for SoC 2003: 261-274 - 2002
- [c5]Inkyu Lee, Marisa López-Vallejo, Syed Aon Mujtaba:
Block processing technique for low power turbo decoder design. VTC Spring 2002: 1025-1029 - 2001
- [p1]Marisa Luisa López-Vallejo, J. M. Fernández Freire, J. Colás:
ED68K. A design framework for the development of digital systems based on MC68000. Computers and Education. Towards an Interconnected Society 2001: 215-225 - 2000
- [c4]Marisa Luisa López-Vallejo, Jesús Grajal, Juan Carlos López:
Constraint-Driven System Partitioning. DATE 2000: 411-416
1990 – 1999
- 1999
- [j2]Marisa Luisa López-Vallejo, Juan Carlos López, Carlos Angel Iglesias:
Hardware-Software Partitioning at the Knowledge Level. Appl. Intell. 10(2-3): 173-184 (1999) - 1998
- [j1]Luis Sánchez Fernández, Gernot Koch, Natividad Martínez Madrid, María Luisa López Vallejo, Carlos Delgado Kloos, Wolfgang Rosenstiel:
Hardware-Software Prototyping from LOTOS. Des. Autom. Embed. Syst. 3(2-3): 117-148 (1998) - [c3]Marisa Luisa López-Vallejo, Carlos Angel Iglesias, Juan Carlos López:
A Knowledge-based System for Hardware-Software Partitioning. DATE 1998: 914-915 - [c2]Marisa Luisa López-Vallejo, Carlos Angel Iglesias, Juan Carlos López:
Applying the Propose&Revise Strategy to the Hardware-Software Partitioning Problem. IEA/AIE (Vol. 1) 1998: 169-179 - 1996
- [c1]Carlos Carreras, Juan Carlos López, María Luisa López Vallejo, Luis Sánchez, Carlos Delgado Kloos, Natividad Martínez Madrid:
A Co-Design Methodology Based on Formal Specification and High-level Estimation. CODES 1996: 28-35
Coauthor Index
José Luis Ayala
aka: José L. Ayala
aka: José L. Ayala
Pedro Echeverría
aka: Pedro Echeverría Aramendi
aka: Pedro Echeverría Aramendi
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