"Accelerating SAT-based Boolean matching for heterogeneous FPGAs using ..."

Yusuke Matsunaga (2015)

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DOI: 10.1109/ASPDAC.2015.7059014

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Yusuke Matsunaga:
Accelerating SAT-based Boolean matching for heterogeneous FPGAs using one-hot encoding and CEGAR technique. ASP-DAC 2015: 255-260

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