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ORCIDYusuke Matsunaga
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2010 – 2019
- 2019
[c36]Yusuke Matsunaga, Masayoshi Yoshimura:
An Efficient SAT-Attack Algorithm Against Logic Encryption. IOLTS 2019: 44-47- 2017
- [j27]Yusuke Matsunaga:
An Accelerating Technique for SAT-based ATPG. IPSJ Trans. Syst. LSI Des. Methodol. 10: 39-44 (2017) - 2016
- [j26]Yusuke Matsunaga:
Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1374-1380 (2016) - [j25]Yusuke Matsunaga:
A Test Pattern Compaction Method Using SAT-Based Fault Grouping. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2302-2309 (2016) - 2015
- [c35]Yusuke Matsunaga:
Accelerating SAT-based Boolean matching for heterogeneous FPGAs using one-hot encoding and CEGAR technique. ASP-DAC 2015: 255-260 - 2014
- [j24]Yusuke Matsunaga:
Synthesis Algorithm for Parallel Index Generator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2451-2458 (2014) - [c34]Yusuke Matsunaga:
Synthesis algorithm of parallel index generation units. DATE 2014: 1-6 - 2013
- [j23]Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga:
An Exact Approach for GPC-Based Compressor Tree Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2553-2560 (2013) - [j22]Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga:
Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 6: 127-134 (2013) - 2012
- [j21]Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga:
An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits. Inf. Media Technol. 7(2): 593-600 (2012) - [j20]Taiga Takata, Yusuke Matsunaga:
A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 5: 55-62 (2012) - [j19]Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga:
An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 5: 63-70 (2012) - [c33]Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura
, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS 2012: 138-141 - 2011
- [j18]Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga:
Multi-Operand Adder Synthesis Targeting FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2579-2586 (2011) - [c32]Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga:
A Soft Error Tolerance Estimation Method for Sequential Circuits. DFT 2011: 268-276 - [c31]Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS 2011: 151-156 - [c30]Taiga Takata, Yusuke Matsunaga:
A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits. IOLTS 2011: 246-251 - [c29]Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga:
Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. ISLPED 2011: 217-222 - 2010
- [c28]Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga:
Multi-operand adder synthesis on FPGAs using generalized parallel counters. ASP-DAC 2010: 337-342 - [c27]Taiga Takata, Yusuke Matsunaga:
A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only). FPGA 2010: 289
2000 – 2009
- 2009
- [j17]Taiga Takata, Yusuke Matsunaga:
Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3268-3275 (2009) - [j16]Sho Kodama, Yusuke Matsunaga:
Binding Refinement for Multiplexer Reduction. Inf. Media Technol. 4(2): 190-199 (2009) - [j15]Sho Kodama, Yusuke Matsunaga:
Binding Refinement for Multiplexer Reduction. IPSJ Trans. Syst. LSI Des. Methodol. 2: 43-52 (2009) - [j14]Taiga Takata, Yusuke Matsunaga:
Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs. IPSJ Trans. Syst. LSI Des. Methodol. 2: 200-211 (2009) - [j13]Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga:
Framework for Parallel Prefix Adder Synthesis Considering Switching Activities. IPSJ Trans. Syst. LSI Des. Methodol. 2: 212-221 (2009) - [c26]Taiga Takata, Yusuke Matsunaga:
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs. ACM Great Lakes Symposium on VLSI 2009: 351-356 - 2008
- [j12]Tsuyoshi Sadakata, Yusuke Matsunaga:
A Behavioral Synthesis Method with Special Functional Units. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(4): 1084-1091 (2008) - [j11]Makoto Sugihara, Yusuke Matsunaga, Kazuaki J. Murakami:
Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3451-3460 (2008) - [c25]Tsuyoshi Sadakata, Yusuke Matsunaga:
An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis. ASP-DAC 2008: 32-35 - [c24]Taiga Takata, Yusuke Matsunaga:
Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs. ASP-DAC 2008: 144-147 - [c23]Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga:
Synthesis of parallel prefix adders considering switching activities. ICCD 2008: 404-409 - 2007
- [j10]Yusuke Matsunaga:
Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(4): 705-706 (2007) - [j9]Tsuyoshi Sadakata, Yusuke Matsunaga:
A Simultaneous Module Selection, Scheduling, and Allocation Method Considering Operation Chaining with Multi-Functional Units. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(4): 792-799 (2007) - [j8]Makoto Sugihara, Kenta Nakamura, Yusuke Matsunaga, Kazuaki J. Murakami:
Technology Mapping Technique for Increasing Throughput of Character Projection Lithography. IEICE Trans. Electron. 90-C(5): 1012-1020 (2007) - [j7]Yusuke Matsunaga:
Special Section on VLSI Design and CAD Algorithms. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2649-2650 (2007) - [j6]Taeko Matsunaga, Yusuke Matsunaga:
Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2770-2777 (2007) - [c22]Taeko Matsunaga, Yusuke Matsunaga:
Area minimization algorithm for parallel prefix adders under bitwise delay constraints. ACM Great Lakes Symposium on VLSI 2007: 435-440 - 2006
- [j5]Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura:
Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment. IEICE Trans. Electron. 89-C(3): 377-383 (2006) - [c21]Masayoshi Yoshimura, Yusuke Matsunaga:
Development of practical ATPG tool with flexible interface. ATS 2006: 129 - [c20]Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura:
A character size optimization technique for throughput enhancement of character projection lithography. ISCAS 2006 - 2005
- [c19]Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura:
Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems. SoC 2005: 137-140 - 2004
- [c18]Hiroyuki Higuchi, Yusuke Matsunaga:
Enhancing the performance of multi-cycle path analysis in an industrial setting. ASP-DAC 2004: 192-197 - [c17]Makoto Sugihara, Kazuaki J. Murakami, Yusuke Matsunaga:
Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. ISVLSI 2004: 179-186 - 2002
- [j4]Yusuke Matsunaga:
An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2715-2724 (2002) - [c16]Ei Ando, Masafumi Yamashita, Toshio Nakata, Yusuke Matsunaga:
The statistical longest path problem and its application to delay analysis of logical circuits. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 134-139
1990 – 1999
- 1998
- [c15]Yusuke Matsunaga:
On accelerating pattern matching for technology mapping. ICCAD 1998: 118-122 - 1996
- [c14]Hiroyuki Higuchi, Yusuke Matsunaga:
A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines. DAC 1996: 463-466 - [c13]Yusuke Matsunaga:
An Efficient Equivalence Checker for Combinational Circuits. DAC 1996: 629-634 - 1995
- [j3]Yusuke Matsunaga:
A New Algorithm for Boolean Matching Utilizing Structural Information. IEICE Trans. Inf. Syst. 78-D(3): 219-223 (1995) - [c12]Hiroyuki Higuchi, Yusuke Matsunaga:
Implicit prime compatible generation for minimizing incompletely specified finite state machines. ASP-DAC 1995 - 1994
- [c11]Yutaka Tamiya, Yusuke Matsunaga, Masahiro Fujita:
LP based cell selection with constraints of timing, area, and power consumption. ICCAD 1994: 378-381 - 1993
- [j2]Masahiro Fujita, Hisanori Fujisawa, Yusuke Matsunaga:
Variable ordering algorithms for ordered binary decision diagrams and their evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1): 6-12 (1993) - [c10]Yusuke Matsunaga, Patrick C. McGeer, Robert K. Brayton:
On Computing the Transitive Closure of a State Transition Relation. DAC 1993: 260-265 - 1991
- [c9]Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita:
A Resynthesis Approach for Network Optimization. DAC 1991: 458-463 - [c8]Masahiro Fujita, Yusuke Matsunaga, Taeko Kakuda:
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. EURO-DAC 1991: 50-54 - [c7]Masahiro Fujita, Yusuke Matsunaga:
Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs. ICCAD 1991: 560-563 - 1990
- [c6]Hitomi Sato, Yoshihiro Yasue, Yusuke Matsunaga, Masahiro Fujita:
Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams. DAC 1990: 284-289 - [c5]Masahiro Fujita, Yusuke Matsunaga, Takeo Kakuda:
Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. ICCAD 1990: 38-41 - [c4]Yusuke Matsunaga, Masahiro Fujita, Takeo Kakuda:
Multi-Level Logic Minimization Across Latch Boundaries. ICCAD 1990: 406-409 - [c3]Hitomi Sato, Norikazu Takahashi, Yusuke Matsunaga, Masahiro Fujita:
Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams. ICCD 1990: 286-290
1980 – 1989
- 1989
- [c2]Yusuke Matsunaga, Masahiro Fujita:
Multi-level logic optimization using binary decision diagrams. ICCAD 1989: 556-559 - 1988
- [c1]Fumihiro Maruyama, Taeko Kakuda, Yusuke Matsunaga, Yoriko Minoda, Shuho Sawada, Nobuaki Kawato:
co-LODEX: A Cooperative Expert System for Logic design. FGCS 1988: 1299-1306 - 1986
- [j1]Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki:
A Hardware Maze Router with Application to Interactive Rip-Up and Reroute. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(4): 466-476 (1986)
Coauthor Index
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