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"A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR."
Thomas Froehlich, Vivek Sharma, Markus Bingesser (2010)
- Thomas Froehlich, Vivek Sharma, Markus Bingesser:
A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR. DATE 2010: 706-710

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