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ORCID"On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry."
Haile Yu, Qiang Xu, Philip Heng Wai Leong (2011)
- Haile Yu, Qiang Xu
, Philip Heng Wai Leong:
On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry. FPL 2011: 539-544
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