Stop the war!
Остановите войну!
for scientists:
default search action
"Clock-aware ultrascale FPGA placement with machine learning routability ..."
Chak-Wa Pui et al. (2017)
- Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu:
Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper). ICCAD 2017: 929-936
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.