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"A high performance full pipelined arquitecture of MLP Neural Networks in FPGA."

Antonyus Pyetro do Amaral Ferreira, Edna Natividade da Silva Barros (2010)

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DOI: 10.1109/ICECS.2010.5724619

access: closed

type: Conference or Workshop Paper

metadata version: 2019-10-19

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  - conf/icecsys/FerreiraB10
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  - https://dblp.org/rec/conf/icecsys/FerreiraB10
Antonyus Pyetro do Amaral Ferreira, Edna Natividade da Silva Barros:
A high performance full pipelined arquitecture of MLP Neural Networks in FPGA. ICECS 2010: 742-745

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