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ORCID17th ICECS 2010: Athens, Greece
- 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010. IEEE 2010, ISBN 978-1-4244-8155-2
- Costas Efstathiou:
Efficient modulo 2N+1 subtractors for weighted operands. 1-4 - Konstantinos Manolopoulos, Dionysios I. Reisis, Vassilios A. Chouliaras:
An efficient dual-mode floating-point Multiply-Add Fused Unit. 5-8 - Ioannis Kouretas
, Vassilis Paliouras:
RNS multi-voltage low-power multiply-add unit. 9-12 - Giuseppe Caruso, Daniela Di Sclafani:
Analysis of compressor architectures in MOS current-mode logic. 13-16 - Fahad Qureshi, Mario Garrido, Oscar Gustafsson:
Alternatives for low-complexity complex rotators. 17-20 - Manuel Pedro, Juan Antonio Gómez Galán, Trinidad Sanchez-Rodriguez, Raúl Jiménez, Clara Isabel Luján-Martínez, Ramón González Carvajal:
A compact voltage-controlled transconductor with high linearity. 21-24 - Edinei Santin, Michael Figueiredo, Rui Santos-Tavares, João Goes, Luís B. Oliveira:
Fast-settling low-power two-stage self-biased CMOS amplifier using feedforward-regulated cascode devices. 25-28 - Syed Ahmed Aamir, J. Jacob Wikner:
A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-NM CMOS. 29-32 - Shi-ming Deng, Herve Mathez, Denis Dauvergne, Guo-Neng Lu:
16-channel readout ASIC for a hodoscope. 33-36 - Michael Pehl, Michael Zwerger, Helmut E. Graeb:
Sizing analog circuits using an SQP and Branch and Bound based approach. 37-40 - Francesco Brandonisio, Michael Peter Kennedy, Franco Maloberti:
First Order Noise Shaping Local-Oscillator Based Time-to-Digital Converter. 41-44 - Antonio J. Ginés, Ricardo Doldán, Adoración Rueda, Eduardo J. Peralías:
Power optimization of CMOS programmable gain amplifiers with high dynamic range and common-mode feed-forward circuit. 45-48 - Hervé Barthélemy, Edith Kussener, Sylvain Bourdel, Wenceslas Rahajandraibe:
Frequency down-conversion with complementary-MOS inverters. 49-52 - Chiou-Bang Chen, Horng-Yuan Shih:
A 400 MHz 0.934ps rms jitter multiplying delay lock loop in 90-nm CMOS process. 53-56 - Sébastien Fregonese, Cristell Maneux, Thomas Zimmer:
From nanoscale technology scenarios to compact device models for ambipolar devices. 57-61 - Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Giovanni Betti Beneventi, Fabien Clermidy, Luca Perniola:
Emerging memory technologies for reconfigurable routing in FPGA architecture. 62-65 - Ian O'Connor, Kotb Jabeur, David Navarro, Nataliya Yakymets, Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Fabien Clermidy:
Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics. 66-69 - Michele De Marchi, Shashikanth Bobba, M. Haykel Ben Jamaa, Giovanni De Micheli:
Synthesis of regular computational fabrics with ambipolar CNTFET technology. 70-73 - Thierry Taris, Aya Mabrouki, Hassene Kraimia, Yann Deval, Jean-Baptiste Bégueret:
Reconfigurable Ultra Low Power LNA for 2.4GHz Wireless Sensor Networks. 74-77 - Anh-Tuan Phan, Ronan Farrell:
Reconfigurable multiband multimode LNA for LTE/GSM, WiMAX, and IEEE 802.11.a/b/g/n. 78-81 - Vasilis Papageorgiou, Spyros Vlassis:
CMOS LNA optimization techniques: Comparative study. 82-85 - Stefan Kaehlert, Dirk Bormann, Ralf Wunderlich, Stefan Heinen:
A Variable Gain Multiband Shunt Feedback LNA for LTE. 86-89 - Ignacio Gil, Raúl Fernández, Javier J. Sieiro, José María López-Villegas:
Optimized passive devices for low-power LNA design. 90-93 - Ryan Helinski, Thomas LeBoeuf, Colby Hoffman, Payman Zarkesh-Ha:
A linear digital VCO for Clock Data Recovery (CDR) applications. 98-101 - Manohar Nagaraju, Wei Wu, Cameron T. Charles:
Process-variation tolerant design techniques for multiphase clock generation. 102-105 - Yo-Hao Tu, Hsiang-Hao Chang, Cheng-Liang Hung, Kuo-Hsing Cheng:
A 3 GHz DLL-based clock generator with stuck locking protection. 106-109 - Younghoon Kim, Jungwon Jeon, Kyuik Cho, Daeyun Kim, Joonho Moon, Minkyu Song:
Design of a 7-bit 1GSPS folding-interpolation A/D converter with self-calibration technique. 110-113 - Armin Jalili, Sayed Masoud Sayedi, J. Jacob Wikner, Kent Palmkvist, Mark Vesterbacka:
Calibration of high-resolution flash ADCS based on histogram test methods. 114-117 - Victor R. Gonzalez-Diaz, Edoardo Bonizzoni, Franco Maloberti:
Pseudorandom sequence generation for mismatch analog compensation of ADCs. 118-121 - Gun-Hee Yun, Min-Kyu Kim, Jong-Boo Kim, Min-Seok Shin, Oh-Kyong Kwon:
A low-power 12-bit 2nd-order Σ-Δ analog-to-digital converter for CMOS image sensors. 122-125 - Ashish Rajshekhar Chalak, Sudip Misra, Mohammad S. Obaidat:
A cluster-head selection algorithm for Wireless Sensor Networks. 130-133 - Nejah Missaoui, Inès Kammoun, Mohamed Siala:
An efficient procedure for packet collision resolution in wireless slotted ALOHA MIMO systems. 134-137 - Tarek K. Refaat, Ramez M. Daoud, Hassanein H. Amer, Mai M. Hassan, Omneya M. Sultan:
Workcell concatenation using wifi-based Wireless Networked Control Systems. 138-141 - Sanjay K. Dhurandher, Mohammad S. Obaidat, Khushboo Diwakar:
A mechanism for reducing congestion while routing bulky data in Mobile Ad Hoc Networks. 142-145 - Jorge L. Tonfat, Ricardo Reis:
Design and verification of a layer-2 Ethernet MAC classification engine for a Gigabit Ethernet switch. 146-149 - Mahsa T. Pourazad, Panos Nasiopoulos, Ali Bashashati:
Random forests-based 2D-to-3D video conversion. 150-153 - Mohamad Adnan Al-Alaoui:
Direct approach to image edge detection using differentiators. 154-157 - Aicha-Baya Goumeidane, Mohammed Khamadja:
Error measures for segmentation results: Evaluation on synthetic images. 158-161 - Di Xu, Lino Coria-Mendoza, Panos Nasiopoulos:
Guidelines for capturing high quality stereoscopic content based on a systematic subjective evaluation. 162-165 - Sami Mahersi, Hassène Mnif, Mourad Loulou:
Calibration of input-match and its center frequency for an inductively degenerated low noise amplifier. 166-169 - Amneh Akour, Waleed Khalil, Mohammed Ismail:
Sub-THz high gain wide-band low noise amplifiers in 90nm RF CMOS technology. 174-177 - Dimitrios Mavridis, Michail Papamichail, Grigorios Kalivas, George D. Papadopoulos:
Inductive coupling for imbalance improvement in a UWB balun employed in a folded cascode mixer. 178-181 - Kianoush Souri, Hossein Shamsi, Sarvenaz Samadian, Hossein Mirzaie:
A 109dB PSRR, 31µW fully-MOSFET bandgap voltage reference in 0.13µm CMOS technology. 182-185 - Casmin Popa:
Low-area tunable CMOS resistor with improved linearity. 190-193 - Bhaba Priyo Das, Neville Watson, Yonghe Liu:
Electronically tunable PLL controller design using OTA. 198-202 - Lubomír Brancík:
Technique of 3D NILT based on complex Fourier series and quotient-difference algorithm. 203-206 - Fernando Castaño, Guido Torelli, Raquel Pérez-Aloe, Juan M. Carrillo:
Low-voltage rail-to-rail bulk-driven CMFB network with improved gain and bandwidth. 207-210 - Yngvar Berg, Mehdi Azadmehr:
Reconfigurable pseudo floating-gate analog circuits. 211-214 - Robert Priewasser, Matteo Agostinelli, Stefano Marsili, Mario Huemer:
Digitally-controlled DC-DC converter with variable switching frequency. 219-222 - João Paulo Carmo, José Carlos Ribeiro, João F. Ribeiro, Manuel F. Silva, Paulo Mateus Mendes, José Higino Correia:
433 MHz implantable wireless stimulation of spinal nerves. 223-226 - Nicolas Pillet, Mohsen Ayachi, Vincent Frick, Hervé Berviller, Jacques Felblinger, Jean-Philippe Blonde:
A complete device dedicated to ECG signal measurement with integrated 3D Hall sensor for signal correction. 227-230 - Dobromir Filip, Orly Yadid-Pecht, Martin P. Mintchev:
Progress in self-stabilizing capsules for imaging of the large intestine. 231-234 - Domien Nowicki, Luc Claesen:
SoC architecture for real-time interactive painting based on lattice-Boltzmann. 235-238 - Ülkühan Güler, Salih Ergün, Günhan Dündar:
A digital IC Random Number Generator with logic gates only. 239-242 - Harris E. Michail, George Athanasiou, George Makridakis, Costas E. Goutis:
Designs and comparisons of authentication modules for IPSec in configurable and extensible embedded processor. 243-246 - Francarl Galea, Edward Gatt, Owen Casha, Ivan Grech:
Control Unit for a Continuous Variable Transmission for use in an Electric Car. 247-250 - Ludovic Noury, Habib Mehrez:
A flexible realtime system for broadband time-frequency analysis in 130 NM CMOS. 251-254 - Takeaki Matsubara, Vasily G. Moshnyaga, Koji Hashimoto:
A FPGA implementation of low-complexity noise removal. 255-258 - Eduard Fernandez-Alonso, David Castells-Rufas, Sergi Risueño, Jordi Carrabina, Jaume Joven:
A NoC-based multi-{soft}core with 16 cores. 259-262 - Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche:
Handling reconvergent paths using conditional probabilities in combinatorial logic netlist reliability estimation. 263-267 - Soumik Ghosh, Jared Tessier, Magdy A. Bayoumi:
ASPEN: An Asynchronous Signal Processor for Energy Efficient Sensor Nodes. 268-272 - Narendran Narayanaswamy, Alexander Skavantzos, Thanos Stouraitis:
Optimal modulus sets for efficient residue-to-binary conversion using the New Chinese Remainder Theorems. 273-276 - Alexis Alexandropoulos, Fotis Plessas, Michael K. Birbas:
A dynamic DFI-compatible strobe qualification system for Double Data Rate (DDR) physical interfaces. 277-280 - Hamid Reza Pourshaghaghi, José Pineda de Gyvez:
Power-performance optimization using fuzzy control of simultaneous supply voltage and body biasing scaling. 281-284 - Maryam Ashouei, Herman Luijmes, Jan Stuijt, Jos Huisken:
Novel wide voltage range level shifter for near-threshold designs. 285-288 - Sangku Park, Jaehoon Lee, Y. Ryu, J. Kang, B. So, Dohyun Baek:
Gate oxide trap characterization under DC and pulse stress. 289-292 - Yngvar Berg:
Novel high speed and ultra low voltage CMOS flip-flops. 293-296 - Duan Wei, Fan Qi Fei, Huang Kun, Zhang Ge:
VB-DVFS: A new algorithm for power efficiency of CMP with GALS. 297-300 - Ilias Pappas, Dimitrios H. Tassis, Stilianos Siskos, Charalambos A. Dimitriadis:
Characteristics of double-gate polycrystalline silicon thin-film transistors for AMOLED pixel design. 301-304 - Arash Abadian, Mojtaba Lotfizad, Nasser Erfani Majd, Mohammad Bagher Ghaznavi Ghoushchi, H. Mirzaie:
A new low-power and low-complexity all digital PLL (ADPLL) in 180nm and 32nm. 305-310 - Hawraa Amhaz, Gilles Sicard:
X-axis spatial redundancy supression: Contribution to the integration of smart reading techniques in a standard CMOS vision sensor. 311-314 - Mohammed Bougataya, Oussama Berriah, Ahmed Lakhssassi, Adel-Omar Dahmane, Yves Blaquière, Yvon Savaria, Richard Norman, Richard Prytula:
Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuit. 315-318 - Hans Kristian Otnes Berge, Matthias W. Blesken, Snorre Aunet, Ulrich Rückert:
Design of 9T SRAM for dynamic voltage supplies by a multiobjective optimization approach. 319-322 - Josep Sabater, José María Gómez, Manel López:
Towards an IEEE 802.15.4 SDR transceiver. 323-326 - Terence Zarb, Ivan Grech, Edward Gatt, Owen Casha, Joseph Micallef:
Verification of a VHDL GPS baseband processor using a simulink-based test bench generator. 327-330 - Sihem Châabouni, Noura Sellami, Mohamed Siala:
Performance analysis of the MAP turbo-equalizer and mapping optimization for BICM. 331-334 - Ahmed A. Mohamed, Ahmed H. Madian:
A modified Rijndael algorithm and it's implementation using FPGA. 335-338 - Feng Hong, David R. S. Cumming:
Source compensation scheme for reducing impact of variability on differential amplifier in 35nm CMOS. 339-342 - Sahbi Baccar, Timothée Levi, Dominique Dallet, Vladimir Shitikov, François Barbara:
A behavioral and temperature measurements-based modeling of an operational amplifier using VHDL-AMS. 343-346 - George Raikos, Spiridon Vlassis:
0.8V bulk-driven variable gain amplifier. 347-350 - Jordi Madrenas, Daniel Fernández, Jordi Cosp:
A low-voltage current sorting circuit based on 4-T min-max CMOS switch. 351-354 - George Raikos, Spiridon Vlassis:
A versatile technique for linearly tunable transconductors. 355-358 - Lanlan He, Shaodan Ma, Yik-Chung Wu, Tung-Sang Ng:
Data detection for cooperative vehicular communication systems with unknown channels. 359-362 - Vasileios D. Papoutsis, Ioannis G. Fraimis, Stavros A. Kotsopoulos:
Resource allocation algorithm for MIMO-OFDMA systems with minimum resources guarantee. 363-366 - Sanjay K. Dhurandher, Mohammad S. Obaidat, Mukta Gupta:
A reactive Optimized Link State Routing protocol for Mobile ad hoc networks. 367-370 - Alp Oguz, Dominique Morche, Catherine Dehollain, Erkan Nevzat Isa:
Adaptive power reconfigurability for preventing excessive power dissipation in wireless receivers. 371-374 - Eren Soyak, Sotirios A. Tsaftaris, Aggelos K. Katsaggelos:
Tracking-optimal pre- and post-processing for H.264 compression in traffic video surveillance applications. 375-378 - Kazuya Zaitsu, Koji Yamamoto, Yasuto Kuroda, Kazunari Inoue, Shingo Ata, Ikuo Oka:
Hardware implementation of fast forwarding engine using standard memory and dedicated circuit. 379-382 - Vagner S. Rosa, Leandro Max Silva, Sergio Bampi:
High performance architectures for the arithmetic encoder of the H.264/AVC CABAC entropy coder. 383-386 - Nikolaos Kefalas, George Theodoridis:
A high throughput pipelined architecture for H.264/AVC deblocking filter. 387-391 - André Luís Del Mestre Martins, Vagner S. Rosa, Sergio Bampi:
A low-cost hardware architecture binarizer design for the H.264/AVC CABAC entropy coding. 392-395 - Yang Lin, David E. Kotecki:
A 2.9-30.3GHz fourth-harmonic voltage-controlled oscillator in 130nm SiGe BiCMOS technology. 396-399 - Mohammad Niaboli-Guilani, Alireza Saberkari, Reza Meshkin:
A low power low phase noise CMOS voltage-controlled oscillator. 422-425 - Yang Lin, David E. Kotecki:
A 0.8-13.4GHz combined voltage-controlled oscillator with an exclusive-OR in 130nm SiGe BiCMOS. 426-429 - Ioannis Tsioutsios, Vasilis F. Pavlidis, Giovanni De Micheli:
Physical design tradeoffs in power distribution networks for 3-D ICs. 430-433 - Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens, Peter Gillen:
Design and analysis of a novel 8T SRAM cell for adiabatic and non-adiabatic operations. 434-437 - Mohammad Fawaz, Nader Kobrosli, Ahmad Chkeir, Ali Chehab, Ayman I. Kayssi:
Transient current and delay analysis for resistive-open defects in future 16 nm CMOS circuits. 438-441 - Rehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, Siva G. Narendra:
Yield enhancement by tube redundancy in CNFET-based circuits. 442-445 - Lucas C. D'Eça, Robson Nunes de Lima, Ana Isabela Araújo Cunha:
A new architecture of companding integrator for CMOS current-mode analog filters. 446-449 - Cosmin Popa:
Improved linearity CMOS active resistor based on complementary computational circuits. 450-453 - Vasilis Kolios, Costas Psychalinos:
Design of low-voltage log-domain filters with maximized dynamic range. 454-457 - Filomila Kafe, Costas Psychalinos:
Differential voltage class-AB current controlled current conveyor. 458-461 - Manuel Pedro, Juan Antonio Gómez Galán, Trinidad Sanchez-Rodriguez, Fernando Muñoz, Ramón González Carvajal, Antonio J. López-Martín:
A low-pass filter with automatic frequency tuning for a bluetooth receiver. 462-465 - Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin:
Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach. 466-469 - Angelos Spanos, Vassilis Paliouras:
VLSI implementation and performance of turbo decoding stopping criteria. 470-474 - Omar Al-Kharji Al-Ali, Nader Anani, Prasad V. S. Ponnapalli, Mahmoud Al-Qutayri, Saleh R. Al-Araji:
TDTL architecture with fast error correction technique. 475-478 - Brian Fitzgibbon, Michael Peter Kennedy:
Calculation of cycle lengths in higher-order MASH DDSMs with constant inputs. 479-482 - Anne-Sophie Bacquet, Christophe Deknudt, Patrick Corlay, Mohamed Gharbi, François-Xavier Coudoux:
Extension of the DSL coverage area for High Definition IPTV VOD services using H.264 Scalable Video Coding. 483-486 - Marwen Hasnaoui, Maher Belhaj, Mihai Mitrea, Françoise J. Prêteux:
MPEG-4 AVC stream watermarking by ST-mDM techniques. 487-490 - Anne-Sophie Bacquet, Christophe Deknudt, Patrick Corlay, François-Xavier Coudoux, Marc Gazalet:
Low complexity H.264/AVC spatial resolution transcoding in the transform domain. 491-494 - Andy Motten, Luc Claesen:
An on-chip parallel memory architecture for a stereo vision system. 495-498 - Christos Gentsos, Calliope-Louisa Sotiropoulou, Spiridon Nikolaidis, Nikolaos Vassiliadis:
Real-time canny edge detection parallel implementation for FPGAs. 499-502 - Amneh Akour, Waleed Khalil, John L. Volakis, Mohammed Ismail:
A compact model for MM-wave transmission lines and interconnects on lossy CMOS substrates. 503-506 - Chun-Yen Huang, Chin-Chung Nien, Chen-Ming Li, Ya-Chung Yu, Li-Yuan Chang, Jenn-Hwan Tarng:
Novel designs for high-efficiency millimeter-wave zero-bias detectors. 507-510 - Kok Meng Lim, Jiangmin Gu, Yang Lu, Jinna Yan, Wei Meng Lim, Kaixue Ma, Kiat Seng Yeo:
Low power millimeter wave active sige sub-harmonic up-conversion mixer with ultra low driving power. 511-514 - Kazuya Kojima, Yasuhiro Toriyama, Masatoshi Nagayasu, Toru Taniguchi:
Improved design of the BB-SoC which incorporated the ultra high speed multi level QAM modem for MM-wave radio systems, and its performance. 515-518 - Ashoka Visweswara Sathanur, Jos Huisken, Jan Stuyt, Harmke de Groot:
Activity profile driven simultaneous vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designs. 519-522 - Khalid Latif, Tiberiu Seceleanu, Cristina Cerschi Seceleanu, Hannu Tenhunen:
Resource-aware task allocation and scheduling for segbus platform. 523-526 - Harry Sidiropoulos, Kostas Siozios, Dimitrios Soudris:
NAROUTO: An open-source framework for supporting architecture-level exploration at heterogeneous FPGAS. 527-530 - Ghizlane Lhairech-Lebreton, Philippe Coussy, Dominique Heller, Eric Martin:
Bitwidth-aware high-level synthesis for designing low-power DSP applications. 531-534 - Ioannis Koutras, Antonis Papanikolaou, George Economakos, Dimitrios Soudris:
BIT-width exploration over 3D architectures using high-level synthesis. 535-538