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"Measuring SET pulsewidths in logic gates using digital infrastructure."

Varadan Savulimedu Veeravalli, Andreas Steininger, Ulrich Schmid (2014)

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DOI: 10.1109/ISQED.2014.6783331

access: closed

type: Conference or Workshop Paper

metadata version: 2020-09-05

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Varadan Savulimedu Veeravalli, Andreas Steininger, Ulrich Schmid:
Measuring SET pulsewidths in logic gates using digital infrastructure. ISQED 2014: 236-242

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