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"A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in ..."

Raul Cernea et al. (2008)

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DOI: 10.1109/ISSCC.2008.4523236

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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  dblp key:
  - conf/isscc/CerneaPMCLLTTNLHPHZKNKHLDHYLSLPYTPLCAFMKLICLHPMQ08
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  persistent URL:
  - https://dblp.org/rec/conf/isscc/CerneaPMCLLTTNLHPHZKNKHLDHYLSLPYTPLCAFMKLICLHPMQ08
Raul Cernea, Long Pham, Farookh Moogat, Siu Lung Chan, Binh Le, Yan Li, Shouchang Tsao, Taiyuan Tseng, Khanh Nguyen, Jason Li, Jayson Hu, Jong Park, Cynthia Hsu, Fanglin Zhang, Teruhiko Kamei, Hiroaki Nasu, Phil Kliza, Khin Htoo, Jeffery Lutze, Yingda Dong, Masaaki Higashitani, Junhui Yang, Hung-Szu Lin, Vamshi Sakhamuri, Alan Li, Feng Pan, Sridhar Yadala, Subodh Taigor, Kishan Pradhan, James Lan, Jim Chan, Takumi Abe, Yasuyuki Fukuda, Hideo Mukai, Koichi Kawakami, Connie Liang, Tommy Ip, Shu-Fen Chang, Jaggi Lakshmipathi, Sharon Huynh, Dimitris Pantelakis, Mehrdad Mofidi, Khandker Quader:
A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm. ISSCC 2008: 420-421

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