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"13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and ..."

Jaehyeok Yang et al. (2024)

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DOI: 10.1109/ISSCC49657.2024.10454560

access: closed

type: Conference or Workshop Paper

metadata version: 2024-03-19

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  dblp key:
  - conf/isscc/YangKKPPKCKKPLLLJJJCHKBLPCK24
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  persistent URL:
  - https://dblp.org/rec/conf/isscc/YangKKPPKCKKPLLLJJJCHKBLPCK24
Jaehyeok Yang, Hyeongjun Ko, Kyunghoon Kim, Hyunsu Park, Jihwan Park, Ji-Hyo Kang, Jin-Youp Cha, Seongjin Kim, Youngtaek Kim, Minsoo Park, Gangsik Lee, Keonho Lee, Sanghoon Lee, Gyunam Jeon, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Seonwoo Hwang, Boram Kim, Sang-Yeon Byeon, Sungkwon Lee, Hyeonyeol Park, Joohwan Cho, Jonghwan Kim:
13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry. ISSCC 2024: 232-234

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