"Static Test Compaction for Full-Scan Circuits Based on Combinational Test ..."

Irith Pomeranz, Sudhakar M. Reddy (2003)

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DOI: 10.1109/ICVD.2003.1183159

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Irith Pomeranz, Sudhakar M. Reddy:
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences. VLSI Design 2003: 335-340

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