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"SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor."

Georgios K. Konstadinidis et al. (2016)

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DOI: 10.1109/JSSC.2015.2456902

access: closed

type: Journal Article

metadata version: 2020-08-30

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  - https://dblp.org/rec/journals/jssc/KonstadinidisLS16
Georgios K. Konstadinidis, Hongping Penny Li, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister, Jeffrey Brooks, Ha Pham, Sebastian Turullols, Yifan YangGong, Robert T. Golla, Alan P. Smith, Ali Vahidsafa:
SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor. IEEE J. Solid State Circuits 51(1): 79-91 (2016)

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