"A 15-ns 32*32-b CMOS multiplier with an improved parallel structure."

Masato Nagamatsu et al. (1990)

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DOI: 10.1109/4.52175

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type: Journal Article

metadata version: 2025-01-23

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Masato Nagamatsu, Shigeru Tanaka, Junji Mori, Katsusi Hirano, Tatsuo Noguchi, Kazuhisa Hatanaka:
A 15-ns 32*32-b CMOS multiplier with an improved parallel structure. IEEE J. Solid State Circuits 25(2): 494-497 (1990)

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