![](https://dblp.org/img/logo.ua.320x120.png)
![](https://dblp.org/img/dropdown.dark.16x16.png)
![](https://dblp.org/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.org/img/search.dark.16x16.png)
![search dblp](https://dblp.org/img/search.dark.16x16.png)
default search action
"P4-To-VHDL: Automatic generation of high-speed input and output network ..."
Pavel Benácek et al. (2018)
- Pavel Benácek, Viktor Pus, Hana Kubátová, Tomás Cejka
:
P4-To-VHDL: Automatic generation of high-speed input and output network blocks. Microprocess. Microsystems 56: 22-33 (2018)
![](https://dblp.org/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.