"Event suppression: improving the efficiency of timing simulation for ..."

Srinivas Devadas et al. (1994)

> Home

Details and statistics

DOI: 10.1109/43.285254

access: closed

type: Journal Article

metadata version: 2023-09-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcad/DevadasKMW94
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcad/DevadasKMW94
Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang:
Event suppression: improving the efficiency of timing simulation for synchronous digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(6): 814-822 (1994)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.