"A design-for-testability technique for register-transfer level circuits ..."

Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha (1998)

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DOI: 10.1109/43.712102

access: closed

type: Journal Article

metadata version: 2021-10-14

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Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
A design-for-testability technique for register-transfer level circuits using control/data flow extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8): 706-723 (1998)

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