"A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC ..."

Ching-Lung Su, Tse-Min Chen, Kuo-Hsuan Wu (2013)

> Home

Details and statistics

DOI: 10.1155/2013/529150

access: open

type: Journal Article

metadata version: 2019-06-02

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - journals/vlsi/SuCW13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/vlsi/SuCW13
Ching-Lung Su, Tse-Min Chen, Kuo-Hsuan Wu:
A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation. VLSI Design 2013: 529150:1-529150:10 (2013)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.