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Publication search results
found 25 matches
- 2023
- Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface. IEICE Trans. Electron. 106(7): 391-394 (2023) - Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver. IEEE J. Solid State Circuits 58(7): 2075-2086 (2023) - Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 70(9): 3440-3450 (2023) - Yao-Chung Hsu, Atsutake Kosuge, Rei Sumikawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network. ASP-DAC 2023: 182-183 - Rei Sumikawa, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS. ASP-DAC 2023: 180-181 - Marcel Menner, Stefano Di Cairano, Masaki Hamada, Kota Gushima:
MPC-based Pedestrian Routing for Congestion Balancing. CCTA 2023: 1089-1094 - Ximing Wang, Atsutake Kosuge, Yasuhiro Hayashi, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
Analysis and Design of a 7 Gb/s Rotatable Non-contact Connector with Grid Array Package Application. NEWCAS 2023: 1-4 - Atsutake Kosuge, Rei Sumikawa, Yao-Chung Hsu, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application. VLSI Technology and Circuits 2023: 1-2 - Kota Fujimoto, Takumi Hamada, Hiroshi Fujimoto:
Proposal on Model Based Current Overshoot Suppression of Receiver Side Coil in Drone Wireless Power Transfer System. CoRR abs/2310.17522 (2023) - 2022
- Ibrahim Abdo, Carrel da Gomez, Chun Wang, Kota Hatano, Qi Li, Chenxin Liu, Kiyoshi Yanagisawa, Ashbir Aviat Fadila, Takuya Fujimura, Tsuyoshi Miura, Korkut Kaan Tokgoz, Jian Pang, Hiroshi Hamada, Hideyuki Nosaka, Atsushi Shirane, Kenichi Okada:
A Bi-Directional 300-GHz-Band Phased-Array Transceiver in 65-nm CMOS With Outphasing Transmitting Mode and LO Emission Cancellation. IEEE J. Solid State Circuits 57(8): 2292-2308 (2022) - Kazunori Ohno, Kotaro Sato, Ryunosuke Hamada, Takatomi Kubo, Kazushi Ikeda, Miho Nagasawa, Takefumi Kikusui, Sandeep Kumar Nayak, Shotaro Kojima, Satoshi Tadokoro:
Electrocardiogram Measurement and Emotion Estimation of Working Dogs. IEEE Robotics Autom. Lett. 7(2): 4047-4054 (2022) - Yao-Chung Hsu, Atsutake Kosuge, Rei Sumikawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network. HCS 2022: 1-14 - Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers. HCS 2022: 1-14 - Saito Shibata, Yoshiki Sawabe, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic. ICECS 2022 2022: 1-4 - Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format. NEWCAS 2022: 99-103 - 2021
- Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda:
A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 692-703 (2021) - Tatsuo Omori, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
Sub-10-μm Coil Design for Multi-Hop Inductive Coupling Interface. ASP-DAC 2021: 99-100 - Kota Shiba, Tatsuo Omori, Mototsugu Hamada, Tadahiro Kuroda:
A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS. ASP-DAC 2021: 97-98 - Saito Shibata, Reiji Miura, Yoshiki Sawabe, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna. A-SSCC 2021: 1-3 - Ibrahim Abdo, Carrel da Gomez, Chun Wang, Kota Hatano, Qi Li, Chenxin Liu, Kiyoshi Yanagisawa, Ashbir Aviat Fadila, Jian Pang, Hiroshi Hamada, Hideyuki Nosaka, Atsushi Shirane, Kenichi Okada:
22.2 A 300GHz-Band Phased-Array Transceiver Using Bi-Directional Outphasing and Hartley Architecture in 65nm CMOS. ISSCC 2021: 316-318 - 2020
- Kohei Ando, Kazuhisa Akatsuka, Chaoran Cheng, Tomoya Arakawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
A 50 Mbps/pin 12-input/output 40 nsec Latency Wireless Connector Using a Transmission Line Coupler with Compact SERDES IC in 180 nm CMOS. ICECS 2020: 1-4 - Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda:
A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. ISCAS 2020: 1-5 - 2019
- Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura:
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. IEEE J. Solid State Circuits 54(1): 186-196 (2019) - 2018
- Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura:
QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. ISSCC 2018: 216-218 - 2014
- Kazunori Hasegawa, Kenichi Yamamoto, Hidetaro Yoshida, Kota Hamada, Masanori Tsukuda, Ichiro Omura:
Short-circuit protection for an IGBT with detecting the gate voltage and gate charge. Microelectron. Reliab. 54(9-10): 1897-1900 (2014)
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