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Publication search results
found 68 matches
- 2016
- Cédric Marchand, Lilian Bossuet, Abdelkarim Cherkaoui:
Enhanced TERO-PUF Implementations and Characterization on FPGAs (Abstract Only). FPGA 2016: 282 - Nimish Agashiwala, Satya Prakash Upadhyay, Kia Bazargan:
t-QuadPlace: Timing Driven Quadratic Placement using Quadrisection Partitioning for FPGAs (Abstact Only). FPGA 2016: 284 - Nikolaos Alachiotis, Gabriel Weisz:
High Performance Linkage Disequilibrium: FPGAs Hold the Key. FPGA 2016: 118-127 - Mohammed Alawad, Mingjie Lin:
Stochastic-Based Convolutional Networks with Reconfigurable Logic Fabric (Abstract Only). FPGA 2016: 283 - Shlomi Alkalay, Hari Angepat, Adrian M. Caulfield, Eric S. Chung, Oren Firestein, Michael Haselman, Stephen Heil, Kyle Holohan, Matt Humphrey, Tamás Juhász, Puneet Kaur, Sitaram Lanka, Daniel Lo, Todd Massengill, Kalin Ovtcharov, Michael Papamichael, Andrew Putnam, Raja Seera, Rimon Tadros, Jason Thong, Lisa Woods, Derek Chiou, Doug Burger:
Agile Co-Design for a Reconfigurable Datacenter. FPGA 2016: 15 - Gregg Baeckler:
HyperPipelining of High-Speed Interface Logic. FPGA 2016: 2 - Yu Bai, Mingjie Lin:
Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology (Abstract Only). FPGA 2016: 279 - Sebastien Bellon, Claudio Favi, Miroslaw Malek, Marco Macchetti, Francesco Regazzoni:
Evaluating the Impact of Environmental Factors on Physically Unclonable Functions (Abstract Only). FPGA 2016: 279 - David Boland:
Reducing Memory Requirements for High-Performance and Numerically Stable Gaussian Elimination. FPGA 2016: 244-253 - Yu-Ting Chen, Jason Cong, Zhenman Fang, Peipei Zhou:
ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture (Abstact Only). FPGA 2016: 281 - Derek Chiou:
Intel Acquires Altera: How Will the World of FPGAs be Affected? FPGA 2016: 148 - Guohao Dai, Yuze Chi, Yu Wang, Huazhong Yang:
FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First Search. FPGA 2016: 105-110 - James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). FPGA 2016: 276 - Girish Deshpande, Dinesh K. Bhatia:
An Activity Aware Placement Approach For 3D FPGAs (Abstract Only). FPGA 2016: 277 - Carl Ebeling, Dana How, David M. Lewis, Herman Schmit:
Stratix™ 10 High Performance Routable Clock Networks. FPGA 2016: 64-73 - Henri Fraisse, Abhishek Joshi, Dinesh Gaitonde, Alireza Kaviani:
Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock Network. FPGA 2016: 74-79 - Xitong Gao, John Wickerson, George A. Constantinides:
Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis. FPGA 2016: 234-243 - Ehsan Ghasemi, Paul Chow:
A Scalable Heterogeneous Dataflow Architecture For Big Data Analytics Using FPGAs (Abstract Only). FPGA 2016: 274 - Pingakshya Goswami, Dinesh Bhatia:
Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only). FPGA 2016: 275 - Paul Grigoras, Pavel Burovskiy, Wayne Luk:
CASK: Open-Source Custom Architectures for Sparse Kernels. FPGA 2016: 179-184 - Matthias Hinkfoth, Ralf Salomon:
Increasing the Utility of Self-Calibration Methods in High-Precision Time Measurement Systems (Abstract Only). FPGA 2016: 275 - Safeen Huda, Jason Helge Anderson:
Towards PVT-Tolerant Glitch-Free Operation in FPGAs. FPGA 2016: 90-99 - Shih-Hao Hung, Min-Yu Tsai, Bo-Yi Huang, Chia-Heng Tu:
A Platform-Oblivious Approach for Heterogeneous Computing: A Case Study with Monte Carlo-based Simulation for Medical Applications. FPGA 2016: 42-47 - Mohammed Shaaban Ibraheem, Syed Zahid Ahmed, Khalil Hachicha, Sylvain Hochberg, Patrick Garda:
A Low DDR Bandwidth 100FPS 1080p Video 2D Discrete Wavelet Transform Implementation on FPGA (Abstract Only). FPGA 2016: 274 - Muhammed Al Kadi, Benedikt Janßen, Michael Hübner:
FGPU: An SIMT-Architecture for FPGAs. FPGA 2016: 254-263 - Nachiket Kapre, Deheng Ye:
GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths. FPGA 2016: 185-194 - Vinod Kathail, James Hwang, Welson Sun, Yogesh Chobe, Tom Shui, Jorge Carrillo:
SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoC. FPGA 2016: 4 - Ronak Kogta, Suresh Purini, Ajit Mathew:
Re-targeting Optimization Sequences from Scalar Processors to FPGAs in HLS compilers (Abstract Only). FPGA 2016: 276 - Aaron Landy, Greg Stitt:
Doubling FPGA Throughput via a Soft SerDes Architecture for Full-Bandwidth Serial Pipelining (Abstract Only). FPGA 2016: 282 - Jie Lei, Yu-Ting Chen, Yunsong Li, Jason Cong:
A High-throughput Architecture for Lossless Decompression on FPGA Designed Using HLS (Abstract Only). FPGA 2016: 277
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