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ORCIDGeorge A. Constantinides
George Anthony Constantinides
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- affiliation: Imperial College London, UK
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2020 – today
- 2023
[j71]Ian McInerney
, Eric C. Kerrigan, George A. Constantinides:
Horizon-Independent Preconditioner Design for Linear Predictive Control. IEEE Trans. Autom. Control. 68(1): 580-587 (2023)- [j70]Jianyi Cheng, Estíbaliz Fraca, John Wickerson, George A. Constantinides:
Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets. IEEE Trans. Computers 72(11): 3300-3313 (2023) - [c191]Morteza Rezaalipour, Lorenzo Ferretti, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi:
ErrorEval: an Open-Source Worst-Case-Error Evaluation Framework for Approximate Computing. CF 2023: 393-394 - [c190]Samuel Coward, George A. Constantinides, Theo Drane:
Automating Constraint-Aware Datapath Optimization using E-Graphs. DAC 2023: 1-6 - [c189]Morteza Rezaalipour, Marco Biasion, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi:
A Parametrizable Template for Approximate Logic Synthesis. DSN-W 2023: 175-178 - [c188]Morteza Rezaalipour, Lorenzo Ferretti, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi:
Multi-Metric SMT-Based Evaluation of Worst-Case-Error for Approximate Circuits. DSN-W 2023: 199-202 - [c187]Benjamin Biggs, Christos-Savvas Bouganis, George A. Constantinides:
ATHEENA: A Toolflow for Hardware Early-Exit Network Automation. FCCM 2023: 121-132 - [c186]Martin Langhammer, George A. Constantinides:
eGPU: A 750 MHz Class Soft GPGPU for FPGA. FPL 2023: 277-282 - [c185]Samuel Coward, George A. Constantinides, Theo Drane:
Combining E-Graphs with Abstract Interpretation. SOAP@PLDI 2023: 1-7 - [i30]Samuel Coward, George A. Constantinides, Theo Drane:
Automating Constraint-Aware Datapath Optimization using E-Graphs. CoRR abs/2303.01839 (2023) - [i29]Benjamin Biggs, Christos-Savvas Bouganis, George A. Constantinides:
ATHEENA: A Toolflow for Hardware Early-Exit Network Automation. CoRR abs/2304.08400 (2023) - [i28]Martin Langhammer, George A. Constantinides:
eGPU: A 750 MHz Class Soft GPGPU for FPGA. CoRR abs/2307.08378 (2023) - [i27]Samuel Coward, Emiliano Morini, Bryan Tan, Theo Drane, George A. Constantinides:
Datapath Verification via Word-Level E-Graph Rewriting. CoRR abs/2308.00431 (2023) - [i26]Benjamin Ramhorst, George A. Constantinides, Vladimir Loncar:
FPGA Resource-aware Structured Pruning for Real-Time Neural Networks. CoRR abs/2308.05170 (2023) - [i25]Marta Andronic, George A. Constantinides:
PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference. CoRR abs/2309.02334 (2023) - [i24]Cheng Zhang, Jianyi Cheng, Ilia Shumailov, George A. Constantinides, Yiren Zhao:
Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference? CoRR abs/2310.05079 (2023) - 2022
- [j69]Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, John Wickerson, George A. Constantinides:
Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code. IEEE Trans. Computers 71(4): 933-946 (2022) - [j68]Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson:
DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 628-641 (2022) - [j67]Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi:
A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 840-853 (2022) - [j66]Nadesh Ramanathan, George A. Constantinides, John Wickerson:
A Case for Precise, Fine-Grained Pointer Synthesis in High-Level Synthesis. ACM Trans. Design Autom. Electr. Syst. 27(4): 30:1-30:26 (2022) - [c184]Samuel Coward, George A. Constantinides, Theo Drane:
Automatic Datapath Optimization using E-Graphs. ARITH 2022: 43-50 - [c183]Jianyi Cheng, John Wickerson, George A. Constantinides:
Dynamic C-Slow Pipelining for HLS. FCCM 2022: 1-10 - [c182]Jianyi Cheng, John Wickerson, George A. Constantinides:
Finding and Finessing Static Islands in Dynamically Scheduled Circuits. FPGA 2022: 89-100 - [c181]Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah:
Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. FPGA 2022: 101-111 - [c180]Ruizhe Zhao, Jianyi Cheng, Wayne Luk, George A. Constantinides:
POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations. FPL 2022: 235-242 - [c179]Jianyi Cheng, Lana Josipovic, George A. Constantinides, John Wickerson:
Dynamic Inter-Block Scheduling for HLS. FPL 2022: 243-252 - [c178]Xuefei He, Jianyi Cheng, George A. Constantinides:
Area-Efficient Memory Scheduling for Dynamically Scheduled High-Level Synthesis. FPT 2022: 1-4 - [c177]Sina Boroumand, Christos-Savvas Bouganis, George A. Constantinides:
MIDAS: Mutual Information Driven Approximate Synthesis. ISVLSI 2022: 50-55 - [i23]Benjamin Biggs, Ian McInerney, Eric C. Kerrigan, George A. Constantinides:
High-level Synthesis using the Julia Language. CoRR abs/2201.11522 (2022) - [i22]Samuel Coward, George A. Constantinides, Theo Drane:
Abstract Interpretation on E-Graphs. CoRR abs/2203.09191 (2022) - [i21]Samuel Coward, George A. Constantinides, Theo Drane:
Automatic Datapath Optimization using E-Graphs. CoRR abs/2204.11478 (2022) - [i20]Samuel Coward, George A. Constantinides, Theo Drane:
Combining E-Graphs with Abstract Interpretation. CoRR abs/2205.14989 (2022) - 2021
- [j65]He Li, Ian McInerney, James J. Davis, George A. Constantinides:
Digit Stability Inference for Iterative Methods Using Redundant Number Representation. IEEE Trans. Computers 70(7): 1074-1080 (2021) - [j64]Nadesh Ramanathan, George A. Constantinides, John Wickerson:
Global Analysis of C Concurrency in High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 24-37 (2021) - [c176]Sina Boroumand, Christos-Savvas Bouganis, George A. Constantinides:
Learning Boolean Circuits from Examples for Approximate Logic Synthesis. ASP-DAC 2021: 524-529 - [c175]George A. Constantinides, Fredrik Dahlqvist, Zvonimir Rakamaric, Rocco Salvia:
Rigorous Roundoff Error Analysis of Probabilistic Floating-Point Computations. CAV (2) 2021: 626-650 - [c174]Jianyi Cheng, John Wickerson, George A. Constantinides:
Probabilistic Scheduling in High-Level Synthesis. FCCM 2021: 195-203 - [c173]Jianyi Cheng, John Wickerson, George A. Constantinides:
Probabilistic Optimization for High-Level Synthesis. FPGA 2021: 145 - [c172]Jianyi Cheng, John Wickerson, George A. Constantinides:
Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLS. FPL 2021: 341-346 - [c171]Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Jia Jie Lim, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides:
Enabling Binary Neural Network Training on the Edge. EMDL@MobiSys 2021: 37-38 - [i19]Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides:
Enabling Binary Neural Network Training on the Edge. CoRR abs/2102.04270 (2021) - [i18]George A. Constantinides, Fredrik Dahlqvist, Zvonimir Rakamaric, Rocco Salvia:
Rigorous Roundoff Error Analysis of Probabilistic Floating-Point Computations. CoRR abs/2105.13217 (2021) - [i17]Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah:
Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. CoRR abs/2112.02346 (2021) - [i16]Dovydas Joksas, Erwei Wang, Nikolaos Barmpatsalos, Wing H. Ng, Anthony J. Kenyon, George A. Constantinides, Adnan Mehonic:
Nonideality-Aware Training for Accurate and Robust Low-Power Memristive Neural Networks. CoRR abs/2112.06887 (2021) - 2020
- [j63]Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi, Sherief Reda:
Approximate Logic Synthesis: A Survey. Proc. IEEE 108(12): 2195-2213 (2020) - [j62]Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides:
LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. IEEE Trans. Computers 69(12): 1795-1808 (2020) - [j61]He Li, James J. Davis, John Wickerson, George A. Constantinides:
architect: Arbitrary-Precision Hardware With Digit Elision for Efficient Iterative Compute. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 516-529 (2020) - [c170]Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson:
Combining Dynamic & Static Scheduling in High-level Synthesis. FPGA 2020: 288-298 - [c169]Nadesh Ramanathan, George A. Constantinides, John Wickerson:
Precise Pointer Analysis in High-Level Synthesis. FPL 2020: 220-224 - [i15]He Li, Ian McInerney, James J. Davis, George A. Constantinides:
Digit Stability Inference for Iterative Methods Using Redundant Number Representation. CoRR abs/2006.09427 (2020) - [i14]Ian McInerney, Eric C. Kerrigan, George A. Constantinides:
Horizon-independent Preconditioner Design for Linear Predictive Control. CoRR abs/2010.08572 (2020)
2010 – 2019
- 2019
- [j60]Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides:
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. ACM Comput. Surv. 52(2): 40:1-40:39 (2019) - [j59]Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides:
Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 719-732 (2019) - [j58]Bulat Khusainov, Eric C. Kerrigan, George A. Constantinides:
Automatic Software and Computing Hardware Codesign for Predictive Control. IEEE Trans. Control. Syst. Technol. 27(5): 2295-2304 (2019) - [c168]Fredrik Dahlqvist, Rocco Salvia, George A. Constantinides:
A Probabilistic Approach to Floating-Point Arithmetic. ACSSC 2019: 596-602 - [c167]Ian McInerney, Eric C. Kerrigan, George A. Constantinides:
Modeling Round-off Error in the Fast Gradient Method for Predictive Control. CDC 2019: 4331-4336 - [c166]Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi:
Partition and Propagate: an Error Derivation Algorithm for the Design of Approximate Circuits. DAC 2019: 40 - [c165]Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides:
LUTNet: Rethinking Inference in FPGA Soft Logic. FCCM 2019: 26-34 - [c164]Florian Faissole, George A. Constantinides, David B. Thomas:
Formalizing Loop-Carried Dependencies in Coq for High-Level Synthesis. FCCM 2019: 315 - [c163]Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, George A. Constantinides:
EASY: Efficient Arbiter SYnthesis from Multi-threaded Code. FPGA 2019: 142-151 - [c162]Yiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert D. Mullins, Peter Y. K. Cheung, George A. Constantinides, Cheng-Zhong Xu:
Automatic Generation of Multi-Precision Multi-Arithmetic CNN Accelerators for FPGAs. FPT 2019: 45-53 - [c161]Ameer M. S. Abdelhadi, Christos-Savvas Bouganis, George A. Constantinides:
Accelerated Approximate Nearest Neighbors Search Through Hierarchical Product Quantization. FPT 2019: 90-98 - [i13]Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides:
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. CoRR abs/1901.06955 (2019) - [i12]Ian McInerney, Eric C. Kerrigan, George A. Constantinides:
Bounding Computational Complexity under Cost Function Scaling in Predictive Control. CoRR abs/1902.02221 (2019) - [i11]Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides:
LUTNet: Rethinking Inference in FPGA Soft Logic. CoRR abs/1904.00938 (2019) - [i10]George A. Constantinides:
Rethinking Arithmetic for Deep Neural Networks. CoRR abs/1905.02438 (2019) - [i9]He Li, James J. Davis, John Wickerson, George A. Constantinides:
ARCHITECT: Arbitrary-precision Hardware with Digit Elision for Efficient Iterative Compute. CoRR abs/1910.00271 (2019) - [i8]Yiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert D. Mullins, Peter Y. K. Cheung, George A. Constantinides, Cheng-Zhong Xu:
Automatic Generation of Multi-precision Multi-arithmetic CNN Accelerators for FPGAs. CoRR abs/1910.10075 (2019) - [i7]Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides:
LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. CoRR abs/1910.12625 (2019) - [i6]Fredrik Dahlqvist, Rocco Salvia, George A. Constantinides:
A Probabilistic Approach to Floating-Point Arithmetic. CoRR abs/1912.00867 (2019) - 2018
- [j57]Nadesh Ramanathan, John Wickerson, George A. Constantinides:
Scheduling Weakly Consistent C Concurrency for Reconfigurable Hardware. IEEE Trans. Computers 67(7): 992-1006 (2018) - [j56]Junyi Liu, John Wickerson, Samuel Bayliss, George A. Constantinides:
Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1802-1815 (2018) - [j55]James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. ACM Trans. Reconfigurable Technol. Syst. 11(1): 2:1-2:22 (2018) - [c160]Nicolas Brisebarre, George A. Constantinides, Milos Ercezovac, Silviu-Ioan Filip, Matei Istoan, Jean-Michel Muller:
A High Throughput Polynomial and Rational Function Approximations Evaluator. ARITH 2018: 99-106 - [c159]He Li, James J. Davis, John Wickerson, George A. Constantinides:
Digit Elision for Arbitrary-accuracy Iterative Computation. ARITH 2018: 107-114 - [c158]Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Hardware Compilation of Deep Neural Networks: An Overview. ASAP 2018: 1-8 - [c157]Nadesh Ramanathan, George A. Constantinides, John Wickerson:
Concurrency-Aware Thread Scheduling for High-Level Synthesis. FCCM 2018: 101-108 - [c156]Georgios Chatzianastasiou, George A. Constantinides:
An Efficient FPGA-based Axis-Aligned Box Tool for Embedded Computer Graphics. FPL 2018: 343-350 - [c155]James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. IWOCL 2018: 4:1 - [c154]Graeme M. Bragg, Charles Leech, Domenico Balsamo, James J. Davis, Eduardo Wächter, Geoff V. Merrett, George A. Constantinides, Bashir M. Al-Hashimi:
An Application- and Platform-agnostic Runtime Management Framework for Multicore Systems. PECCS 2018: 195-204 - 2017
- [j54]James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. IEEE Des. Test 34(6): 36-45 (2017) - [j53]Felix Winterstein, Kermin Elliott Fleming, Hsin-Jung Yang, George A. Constantinides:
Custom Multicache Architectures for Heap Manipulating Programs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(5): 761-774 (2017) - [j52]Victor Magron, George A. Constantinides, Alastair F. Donaldson:
Certified Roundoff Error Bounds Using Semidefinite Programming. ACM Trans. Math. Softw. 43(4): 34:1-34:31 (2017) - [c153]Junyi Liu, John Wickerson, Samuel Bayliss, George A. Constantinides:
Run fast when you can: Loop pipelining with uncertain and non-uniform memory dependencies. ACSSC 2017: 126-130 - [c152]George Anthony Constantinides:
Algorithms and Arithmetic: Choose Wisely. ARITH 2017: 142-143 - [c151]Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides:
Quantifying error: Extending static timing analysis with probabilistic transitions. DATE 2017: 1486-1491 - [c150]George A. Constantinides:
FPGAs in the Cloud. FPGA 2017: 167 - [c149]Nadesh Ramanathan, Shane T. Fleming, John Wickerson, George A. Constantinides:
Hardware Synthesis of Weakly Consistent C Concurrency. FPGA 2017: 169-178 - [c148]James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
STRIPE: Signal selection for runtime power estimation. FPL 2017: 1-8 - [c147]Junyi Liu, John Wickerson, George A. Constantinides:
Tile size selection for optimized memory reuse in high-level synthesis. FPL 2017: 1-8 - [c146]He Li, James J. Davis, John Wickerson, George A. Constantinides:
architect: Arbitrary-precision constant-hardware iterative compute. FPT 2017: 73-79 - [c145]Felix Winterstein, George A. Constantinides:
Pass a pointer: Exploring shared virtual memory abstractions in OpenCL tools for FPGAs. FPT 2017: 104-111 - [c144]John Wickerson, Mark Batty, Tyler Sorensen, George A. Constantinides:
Automatically comparing memory consistency models. POPL 2017: 190-204 - [i5]Bulat Khusainov, Eric C. Kerrigan, Andrea Suardi, George A. Constantinides:
Nonlinear Predictive Control on a Heterogeneous Computing Platform. CoRR abs/1710.08737 (2017) - [i4]Bulat Khusainov, Eric C. Kerrigan, George A. Constantinides:
Automatic Software and Computing Hardware Co-design for Predictive Control. CoRR abs/1710.08802 (2017) - 2016
- [j51]Felix J. Winterstein, Samuel R. Bayliss, George A. Constantinides:
Separation Logic for High-Level Synthesis. ACM Trans. Reconfigurable Technol. Syst. 9(2): 10:1-10:23 (2016) - [c143]Bulat Khusainov, Eric C. Kerrigan, George A. Constantinides:
Multi-objective Co-design for model predictive control with an FPGA. ECC 2016: 110-115 - [c142]Eric C. Kerrigan, Bulat Khusainov, George A. Constantinides:
What is different about embedded optimization? ECC 2016: 600 - [c141]Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. FCCM 2016: 56-63 - [c140]Junyi Liu, John Wickerson, George A. Constantinides:
Loop Splitting for Efficient Pipelining in High-Level Synthesis. FCCM 2016: 72-79 - [c139]Nadesh Ramanathan, John Wickerson, Felix Winterstein, George A. Constantinides:
A Case for Work-stealing on FPGAs with OpenCL Atomics. FPGA 2016: 48-53 - [c138]Xitong Gao, John Wickerson, George A. Constantinides:
Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis. FPGA 2016: 234-243 - [c137]James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). FPGA 2016: 276 - [c136]Yiren Zhao, John Wickerson, George A. Constantinides:
An efficient implementation of online arithmetic. FPT 2016: 69-76 - [c135]Andrea Picciau, Gordon E. Inggs, John Wickerson, Eric C. Kerrigan, George A. Constantinides:
Balancing Locality and Concurrency: Solving Sparse Triangular Systems on GPUs. HiPC 2016: 183-192 - 2015
- [j50]Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan:
A Low Complexity Scaling Method for the Lanczos Kernel in Fixed-Point Arithmetic. IEEE Trans. Computers 64(2): 303-315 (2015) - [j49]Abid Rafique, George A. Constantinides, Nachiket Kapre:
Communication Optimization of Iterative Sparse Matrix-Vector Multiply on GPUs and FPGAs. IEEE Trans. Parallel Distributed Syst. 26(1): 24-34 (2015) - [j48]Kan Shi, David Boland, George A. Constantinides:
Imprecise Datapath Design: An Overclocking Approach. ACM Trans. Reconfigurable Technol. Syst. 8(2): 6:1-6:23 (2015) - [c134]Eric C. Kerrigan, George A. Constantinides, Andrea Suardi, Andrea Picciau, Bulat Khusainov:
Computer architectures to close the loop in real-time optimization. CDC 2015: 4597-4611 - [c133]David B. Thomas, Shane T. Fleming, George A. Constantinides, Dan R. Ghica:
Transparent linking of compiled software and synthesized hardware. DATE 2015: 1084-1089 - [c132]Andrea Suardi, Eric C. Kerrigan, George A. Constantinides:
Fast FPGA prototyping toolbox for embedded optimization. ECC 2015: 2589-2594 - [c131]Junyi Liu, Samuel Bayliss, George A. Constantinides:
Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS. FCCM 2015: 159-162 - [c130]Eddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk:
Delay-Bounded Routing for Shadow Registers. FPGA 2015: 56-65 - [c129]Felix Winterstein, Kermin Fleming, Hsin-Jung Yang, Samuel Bayliss, George A. Constantinides:
MATCHUP: Memory Abstractions for Heap Manipulating Programs. FPGA 2015: 136-145 - [c128]Xitong Gao, George A. Constantinides:
Numerical Program Optimization for High-Level Synthesis. FPGA 2015: 210-213 - [c127]Shane T. Fleming, David B. Thomas, George A. Constantinides, Dan R. Ghica:
System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System. FPGA 2015: 214-217 - [c126]Shane T. Fleming, Ivan Beretta, David B. Thomas, George A. Constantinides, Dan R. Ghica:
PushPush: Seamless integration of hardware and software objects via function calls over AXI. FPL 2015: 1-8 - [c125]Felix Winterstein, Kermin Fleming, Hsin-Jung Yang, John Wickerson, George A. Constantinides:
Custom-sized caches in application-specific memory hierarchies. FPT 2015: 144-151 - [e4]George A. Constantinides, Deming Chen:
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 22-24, 2015. ACM 2015, ISBN 978-1-4503-3315-3 [contents] - [i3]