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Publication search results
found 68 matches
- 2012
- Kaveh Aasaraai, Andreas Moshovos:
SPREX: A soft processor with Runahead execution. ReConFig 2012: 1-7 - Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
Efficient parallel-pipelined GHASH for message authentication. ReConFig 2012: 1-6 - Jeremy Abramson, Pedro C. Diniz:
Resiliency-aware Scheduling for reconfigurable VLIW processors. ReConFig 2012: 1-7 - Nikolaos Alachiotis, Simon A. Berger, Alexandros Stamatakis:
A versatile UDP/IP based PC ↔ FPGA communication platform. ReConFig 2012: 1-6 - Ashraful Alam, Zain-ul-Abdin, Bertil Svensson:
Parallelization of the estimation algorithm of the 3D structure tensor. ReConFig 2012: 1-6 - Dawood Alnajiar, Masanori Hashimoto, Takao Onoye, Yukio Mitsuyama:
Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices. ReConFig 2012: 1-7 - Hugo A. Andrade, Arkadeb Ghosal, Kaushik Ravindran, Brian L. Evans:
A methodology for the design and deployment of reliable systems on heterogeneous platforms. ReConFig 2012: 1-7 - Jose Hugo Barron-Zambrano, César Torres-Huitzil, Horacio Rostro-González:
Versatile FPGA-based locomotion platform for legged robots. ReConFig 2012: 1-6 - Matthias Birk, Matthias Norbert Balzer, Nicole V. Ruiter, Jürgen Becker:
Comparison of processing performance and architectural efficiency metrics for FPGAs and GPUs in 3D Ultrasound Computer Tomography. ReConFig 2012: 1-7 - Alex A. Birklykke, Yannick Le Moullec, Lars K. Alminde, Ramjee Prasad:
An automated test framework for experimenting with stochastic behavior in reconfigurable logic. ReConFig 2012: 1-6 - Andrey Bogdanov, Elif Bilge Kavun, Elmar Tischhauser, Tolga Yalçin:
Efficient reconfigurable hardware architecture for accurately computing success probability and data complexity of linear attacks. ReConFig 2012: 1-6 - Andrey Bogdanov, Amir Moradi, Tolga Yalçin:
Efficient and side-channel resistant authenticated encryption of FPGA bitstreams. ReConFig 2012: 1-6 - Robin Bonamy, Daniel Chillet, Sébastien Bilavarn, Olivier Sentieys:
Power consumption model for partial and dynamic reconfiguration. ReConFig 2012: 1-8 - David Castells-Rufas, Oscar Vila-Closas, Jordi Carrabina:
Design of a multi-soft-core based Laser Marking controller. ReConFig 2012: 1-6 - Marc-André Daigneault, Jean-Pierre David:
Synchronized-transfer-level design methodology applied to hardware matrix multiplication. ReConFig 2012: 1-7 - Mickaël Dardaillon, Cédric Lauradoux, Tanguy Risset:
Hardware implementation of the GPS authentication. ReConFig 2012: 1-6 - Andy Caley Data, Kent Gilson:
Isolation of behavior design from system implementation. ReConFig 2012: 1-6 - Benedikt Driessen, Tim Güneysu, Elif Bilge Kavun, Oliver Mischke, Christof Paar, Thomas Pöppelmann:
IPSecco: A lightweight and reconfigurable IPSec core. ReConFig 2012: 1-7 - Nashwa Elaraby, Iyad Obeid:
A model design of a 2560-channel neural spike detection platform. ReConFig 2012: 1-6 - Oguzhan Erdem, Aydin Carus, Hoang Le:
Compact trie forest: Scalable architecture for IP lookup on FPGAs. ReConFig 2012: 1-6 - Tannous Frangieh, Peter Athanas:
A design assembly framework for FPGA back-end acceleration. ReConFig 2012: 1-6 - Laurent Gantel, Mohamed El Amine Benkhelifa, Fabrice Lemonnier, François Verdier:
Module relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow. ReConFig 2012: 1-6 - Jaime J. Garnica, Sergio López-Buedo, Víctor López, Javier Aracil, José María Gómez Hidalgo:
A FPGA-based scalable architecture for URL legal filtering in 100GbE networks. ReConFig 2012: 1-6 - Lubos Gaspar, Viktor Fischer, Tim Güneysu, Zouha Cherif Jouini:
Two IP protection schemes for multi-FPGA systems. ReConFig 2012: 1-6 - A. D. Santana Gil, Manuel Hernandez Calviño, Francisco Javier Quiles-Latorre, Ezequiel Herruzo Gomez, José Ignacio Benavides Benítez:
Optimizing the physical implementation of a reconfigurable cache. ReConFig 2012: 1-6 - Christina Gimmler-Dumont, Philipp Schläfer, Norbert Wehn:
FPGA-based rapid prototyping platform for MIMO-BICM design space exploration. ReConFig 2012: 1-7 - Frederik Grüll, Michael Kunz, Michael Hausmann, Udo Kebschull:
An implementation of 3D Electron Tomography on FPGAs. ReConFig 2012: 1-5 - Markus Happe, Hendrik Hangmann, Andreas Agne, Christian Plessl:
Eight ways to put your FPGA on fire - A systematic study of heat generators. ReConFig 2012: 1-6 - Swapnil Haria, Thilan Ganegedara, Viktor K. Prasanna:
Power-efficient and scalable virtual router architecture on FPGA. ReConFig 2012: 1-7 - Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Automatic generation of identical routing pairs for FPGA implemented DPL logic. ReConFig 2012: 1-6
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